 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| LH7A400 Preliminary data sheet FEATURES * 32-bit ARM9TDMITM RISC Core - 16 kB Cache: 8 kB Instruction and 8 kB Data - MMU (Windows CETM Enabled) - Up to 250 MHz; see Table 1 for options * 80 kB On-Chip Static RAM * Programmable Interrupt Controller * External Bus Interface - Up to 125 MHz; see Table 1 for options - Asynchronous SRAM/ROM/Flash - Synchronous DRAM/Flash - PCMCIA - CompactFlash * Clock and Power Management - 32.768 kHz and 14.7456 MHz Oscillators - Programmable PLL * Programmable LCD Controller - Up to 1,024 x 768 Resolution - Supports STN, Color STN, AD-TFT, HR-TFT, TFT - Up to 64 k-Colors and 15 Gray Shades * DMA (10 Channels) - AC97 - MMC - USB * USB Device Interface (USB 2.0, Full Speed) * Synchronous Serial Port (SSP) - Motorola SPITM - Texas Instruments SSI - National MICROWIRETM 32-Bit System-on-Chip * Three Programmable Timers * Three UARTs - Classic IrDA (115 kbit/s) * Smart Card Interface (ISO7816) * Two DC-to-DC Converters * MultiMediaCardTM Interface * AC97 Codec Interface * Smart Battery Monitor Interface * Real Time Clock (RTC) * Up to 60 General Purpose I/Os * Watchdog Timer * JTAG Debug Interface and Boundary Scan * Operating Voltage - 1.8 V Core - 3.3 V Input/Output * 5 V Tolerant Digital Inputs (except oscillator pins) - Oscillator pins P15, P16, R13, and T13 are 1.8 V 10 %. * Operating Temperature: -40C to +85C * 256-ball BGA or 256-ball LFBGA Package DESCRIPTION The LH7A400, powered by an ARM922T, is a complete System-on-Chip with a high level of integration to satisfy a wide range of requirements and expectations. This high degree of integration lowers overall system costs, reduces development cycle time and accelerates product introduction. Table 1. LH7A400 versions PART NUMBER LH7A400N0F076B5 LH7A400N0F000B3A LH7A400N0F000B5 LH7A400N0G000B5 CORE CLOCK 250 MHz/ 245 MHz 200 MHz/ 195 MHz 200 MHz/ 195 MHz 200 MHz/ 195 MHz BUS CLOCK 125 MHz 100 MHz 100 MHz 100 MHz LOW POWER CURRENT BY MODE (TYP.) Run = 250 mA; Halt = 50 mA; Standby = 129 A Run = 125 mA; Halt: 25 mA; Standby = 42 A Run = 125 mA; Halt: 25 mA; Standby = 42 A Run = 125 mA; Halt: 25 mA; Standby = 42 A TEMP. RANGE 0C to +70C/ -40C to +85C 0C to +70C/ -40C to +85C 0C to +70C/ -40C to +85C 0C to +70C/ -40C to +85C Preliminary data sheet 1 LH7A400 NXP Semiconductors 32-Bit System-on-Chip Table 2. Ordering information Package Type number Name LH7A400N0G000B5 LH7A400N0F000B3A LH7A400N0F000B5 LH7A400N0F076B5 BGA256 LFBGA256 LFBGA256 LFBGA256 Description plastic ball grid array package; 256 balls plastic low profile fine-pitch ball grid array package; 256 balls plastic low profile fine-pitch ball grid array package; 256 balls plastic low profile fine-pitch ball grid array package; 256 balls SOT1018-1 SOT1020-1 SOT1020-1 SOT1020-1 Version 2 Rev. 01 -- 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A400 LH7A400 14.7456 MHz 32.768 kHz OSCILLATOR, PLL1 and PLL2, POWER MANAGEMENT, and RESET CONTROL REAL TIME CLOCK WATCHDOG TIMER ARM922T INTERRUPT CONTROLLER STATIC (ASYNCHRONOUS) MEMORY CONTROLLER (SMC) EXTERNAL BUS INTERFACE PCMCIA/CF CONTROLLER SYNCHRONOUS DYNAMIC RAM CONTROLLER (SDMC) LCD AHB BUS 80KB SRAM TIMER (3) GENERAL PURPOSE I/O (60) SYNCHRONOUS SERIAL PORT BATTERY MONITOR INTERFACE UART (3) IrDA INTERFACE USB DEVICE INTERFACE MULTIMEDIACARD INTERFACE ADVANCED AUDIO CODEC (AC97) ADVANCED PERIPHERAL BUS BRIDGE COLOR LCD CONTROLLER DMA CONTROLLER ADVANCED LCD INTERFACE AUDIO CODEC INTERFACE SMART CARD INTERFACE (ISO7816) DC to DC INTERFACE (2) ADVANCED HIGH-PERFORMANCE BUS (AHB) ADVANCED PERPHERAL BUS (APB) LH7A400-1 Figure 1. LH7A400 block diagram Preliminary data sheet Rev. 01 -- 16 July 2007 3 LH7A400 NXP Semiconductors 32-Bit System-on-Chip ball A1 index area 1 A B C D E F G H J K L M N P R T LH7A400 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 002aad223 Transparent top view Figure 2. Pin configuration (BGA256) ball A1 index area 1 A B C D E F G H J K L M N P R T LH7A400 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 002aad224 Transparent top view Figure 3. Pin configuration (LFBGA256) 4 Rev. 01 -- 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A400 Table 3. Functional Pin List BGA PIN G7 F1 K7 M1 M5 T6 R14 M14 J11 J12 F13 B14 E10 B8 H7 G3 K4 N5 P6 T14 R16 N16 K13 H9 C15 A11 E8 A5 F7 E1 J4 P3 T8 K9 L13 E15 D12 A7 H5 M3 L9 T10 N15 H12 B15 C9 G6 LFBGA PIN C10 F9 F11 F14 G8 H13 J9 K15 L7 N6 N8 N12 N13 P11 B8 C6 D5 D13 E8 F7 G13 H9 J14 K7 L8 L10 L12 M11 M14 C4 D7 D10 F4 F10 J4 J8 K8 L6 G7 H4 H8 L4 L9 N3 N7 N10 R5 VSSC Core Ground VDDC Core Power VSS I/O Ring Ground VDD I/O Ring Power SIGNAL DESCRIPTION RESET STATE STANDBY STATE OUTPUT I/O NOTES DRIVE Preliminary data sheet Rev. 01 -- 16 July 2007 5 LH7A400 NXP Semiconductors 32-Bit System-on-Chip Table 3. Functional Pin List (Cont'd) BGA PIN R11 N12 P12 T11 D3 H6 D4 E4 C2 R13 T13 P16 P15 P14 J6 K11 K10 P13 M12 L12 M15 N13 L16 L15 L14 H11 K12 J15 J13 J10 H15 H13 G15 G11 G12 F15 F12 E14 D16 H10 D14 F10 A16 A14 B13 LFBGA PIN P12 M10 R13 N11 E4 D1 E2 F2 D2 R14 R15 N14 M13 M12 J5 P14 P16 N15 N16 L11 L13 L14 K11 L16 K14 J15 J12 J10 H16 H14 H11 G16 G9 G14 G12 F15 E15 D16 F12 E13 D14 E12 B16 D12 A16 SIGNAL VDDA VSSA nPOR nURESET WAKEUP nPWRFL nEXTPWR XTALIN XTALOUT XTAL32IN XTAL32OUT CLKEN PGMCLK nCS0 nCS1 nCS2 nCS3/ nMMSPICS D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 Data Bus LOW LOW 12 mA I/O DESCRIPTION Analog Power for PLL Analog Ground for PLL Power On Reset User Reset; should be pulled HIGH for normal or JTAG operation. Wake Up Power Fail Signal External Power 14.7456 MHz Crystal Oscillator pins. An external clock source can be connected to XTALIN leaving XTALOUT open. 32.768 kHz Real Time Clock Crystal Oscillator pins. An external clock source can be connected to XTAL32IN leaving XTAL32OUT open. External Osc Clock Enable Output Programmable Clock (14.7456 MHz MAX.) Async Memory Chip Select 0 Async Memory Chip Select 1 Async Memory Chip Select 2 * Async Memory Chip Select 3 * MultiMediaCard SPI Mode Chip Select Input Input Input Input Input Input HIGH Input Output LOW LOW HIGH HIGH HIGH HIGH: nCS3 No Change No Change No Change No Change No Change No Change HIGH No Change No Change LOW LOW or HIGH No Change No Change No Change No Change 8 mA 8 mA 12 mA 12 mA 12 mA 12 mA I I I I I I O I O O O O O O O 3 3 3 3 3 RESET STATE STANDBY STATE OUTPUT I/O NOTES DRIVE 6 Rev. 01 -- 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A400 Table 3. Functional Pin List (Cont'd) BGA PIN C13 E12 G10 B12 B11 D11 M16 N14 M13 K16 K15 K14 J8 J16 J14 J9 H16 H14 G16 G14 G13 F16 F14 E16 E13 F11 D15 C16 B16 A15 A13 G8 F8 A8 D8 C8 D10 B10 C10 G9 A10 C14 LFBGA PIN B13 B14 C12 A14 B12 A12 M15 M16 L15 K12 K13 K16 J13 J11 J16 H15 H10 H12 G15 G10 G11 F16 E16 F13 E14 D15 C16 C15 C14 B15 E11 D8 B7 A7 C8 F8 D9 E9 A10 A11 B10 C13 SIGNAL D26 D27 D28 D29 D30 D31 A0/nWE1 A1/nWE2 A2/SA0 A3/SA1 A4/SA2 A5/SA3 A6/SA4 A7/SA5 A8/SA6 A9/SA7 A10/SA8 A11/SA9 A12/SA10 A13/SA11 A14/SA12 A15/SA13 A16/SB0 A17/SB1 A18 A19 A20 A21 A22 A23 A24 A25/SCIO A26/SCCLK A27/SCRST nOE nWE0 nWE3 * Async Memory Address Bus * Smart Card Interface I/O (Data) * Async Memory Address Bus * Smart Card Interface Clock * Async Memory Address Bus * Smart Card Interface Reset Async Memory Output Enable Async Memory Write Byte Enable 0 Async Memory Write Byte Enable 3 LOW: A25 LOW: A26 LOW: A27 HIGH HIGH HIGH LOW: CS6 LOW: CS7 LOW LOW HIGH LOW LOW LOW No Change No Change No Change No Change No Change LOW No Change No Change 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 8 mA 12 mA 12 mA 12 mA I/O I/O O O O O O O O I/O O 2 Asynchronous Address Bus LOW LOW 12 mA O * Async Address Bus * Sync Device Bank Address 0 * Async Address Bus * Sync Device Bank Address 1 LOW LOW LOW LOW 12 mA 12 mA O O * Asynchronous Address Bus * Synchronous Address Bus LOW LOW 12 mA O * Asynchronous Address Bus * Asynchronous Memory Write Byte Enable 1 * Asynchronous Address Bus * Asynchronous Memory Write Byte Enable 2 HIGH: nWE1 HIGH: nWE2 HIGH HIGH 12 mA 12 mA O O Data Bus LOW LOW 12 mA I/O DESCRIPTION RESET STATE STANDBY STATE OUTPUT I/O NOTES DRIVE * Async Memory Chip Select 6 CS6/SCKE1_2 * Sync Memory Clock Enable 1 or 2 CS7/SCKE0 SCKE3 SCLK nSCS0 * Async Memory Chip Select 7 * Sync Memory Clock Enable 0 Sync Memory Clock Enable 3 Sync Memory Clock Sync Memory Chip Select 0 Preliminary data sheet Rev. 01 -- 16 July 2007 7 LH7A400 NXP Semiconductors 32-Bit System-on-Chip Table 3. Functional Pin List (Cont'd) BGA PIN D13 E11 A12 C12 C11 F9 A9 B9 D9 E9 J5 LFBGA PIN A15 D11 E10 A13 B11 C11 C9 A9 B9 A8 K1 SIGNAL nSCS1 nSCS2 nSCS3 nSWE nCAS nRAS DQM0 DQM1 DQM2 DQM3 DESCRIPTION Sync Memory Chip Select 1 Sync Memory Chip Select 2 Sync Memory Chip Select 3 Sync Memory Write Enable Sync Memory Column Address Strobe Signal Sync Memory Row Address Strobe Signal Sync Memory Data Mask 0 Sync Memory Data Mask 1 Sync Memory Data Mask 2 Sync Memory Data Mask 3 RESET STATE HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH Input: PA0 STANDBY STATE No Change No Change No Change No Change No Change No Change No Change No Change No Change No Change No Change OUTPUT I/O NOTES DRIVE 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 12 mA 8 mA O O O O O O O O O O I/O * GPIO Port A PA0/LCDVD16 * LCD Data bit 16. This CLCDC output signal is always LOW. * GPIO Port A PA1/LCDVD17 * LCD Data bit 17. This CLCDC output signal is always LOW. PA2 PA3 PA4 PA5 PA6 PA7 PB0/ UARTRX1 * GPIO Port B * UART1 Receive Data Input GPIO Port A K1 K2 K3 K5 L1 L2 L3 L4 K2 K3 K4 K6 K5 L1 L2 L3 Input: PA1 No Change 8 mA I/O I/O I/O I/O I/O I/O I/O Input No Change 8 mA Input: PB0 No Change LOW if PINMUX: UART3CON = 1 (bit 3); otherwise No Change No Change No Change No Change No Change 8 mA I/O L5 M1 PB1/UARTTX3 * GPIO Port B * UART3 Transmit Data Out Input: PB1 8 mA I/O L7 M2 M4 N1 M2 M3 L5 N1 PB2/ UARTRX3 PB3/ UARTCTS3 PB4/ UARTDCD3 PB5/ UARTDSR3 PB6/SWID/ SMBD PB7/ SMBCLK PC0/ UARTTX1 PC1/LCDPS PC2/ LCDVDDEN PC3/LCDREV PC4/ LCDSPS * GPIO Port B * UART3 Receive Data In * GPIO Port B * UART3 Clear to Send * GPIO Port B * UART3 Data Carrier Detect * GPIO Port B * UART3 Data Set Ready * GPIO Port B * Single Wire Data * Smart Battery Data * GPIO Port B * Smart Battery Clock * GPIO Port C * UART1 Transmit Data Output * GPIO Port C * HR-TFT Power Save * GPIO Port C * HR-TFT Power Sequence Control * GPIO Port C * HR-TFT Gray Scale Voltage Reverse * GPIO Port C * HR-TFT Reset Row Driver Counter Input: PB2 Input: PB3 Input: PB4 Input: PB5 8 mA 8 mA 8 mA 8 mA I/O I/O I/O I/O N2 N2 Input: PB6 No Change 8 mA I/O N3 P1 P2 R1 K6 L8 M4 P1 P2 R1 M5 P3 Input: PB7 LOW: PC0 LOW: PC1 LOW: PC2 LOW: PC3 LOW: PC4 No Change No Change No Change No Change No Change No Change 8 mA 12 mA 12 mA 12 mA 12 mA 12 mA I/O I/O I/O I/O I/O I/O 7 8 Rev. 01 -- 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A400 Table 3. Functional Pin List (Cont'd) BGA PIN T1 T2 R2 M11 L11 K8 N11 R9 T9 P10 R10 L10 N10 M9 M10 LFBGA PIN N4 R2 N5 M9 K10 P10 T11 T12 R11 R12 T13 T9 K9 T10 R10 SIGNAL PC5/ LCDCLS PC6/LCDHRLP PC7/ LCDSPL PD0/LCDVD8 PD1/LCDVD9 PD2/LCDVD10 PD3/LCDVD11 * GPIO Port D PD4/LCDVD12 * LCD Video Data Bus PD5/LCDVD13 PD6/LCDVD14 PD7/LCDVD15 PE0/LCDVD4 PE1/LCDVD5 PE2/LCDVD6 PE3/LCDVD7 * GPIO Port F * External FIQ Interrupt. Interrupts can be level or edge triggered and are internally debounced. * GPIO Port F * External IRQ Interrupts. Interrupts can be level or edge triggered and are internally debounced. * GPIO Port F * External IRQ Interrupt. Interrupts can be level or edge triggered and are internally debounced. * GPIO Port F * External IRQ Interrupt. Interrupts can be level or edge triggered and are internally debounced. * Smart Card Supply Voltage Enable * GPIO Port F * External IRQ Interrupt. Interrupts can be level or edge triggered and are internally debounced. * Smart Card Detection * GPIO Port F * External IRQ Interrupt. Interrupts can be level or edge triggered and are internally debounced. * Ready for Card 1 for PC Card (PCMCIA or CF) in single or dual card mode * GPIO Port F * External IRQ Interrupt. Interrupts can be level or edge triggered and are internally debounced. * Ready for Card 2 for PC Card (PCMCIA or CF) in single or dual card mode * GPIO Port G * Output Enable for PC Card (PCMCIA or CF) in single or dual card mode * GPIO Port E * LCD Video Data Bus DESCRIPTION * GPIO Port C * HR-TFT Row Driver Clock * GPIO Port C * LCD Latch Pulse * GPIO Port C * LCD Start Pulse Left RESET STATE LOW: PC5 LOW: PC6 LOW: PC7 LOW: PD0 LOW: PD1 LOW: PD2 LOW: PD3 LOW: PD4 LOW: PD5 LOW: PD6 LOW: PD7 Input: PE0 Input: PE1 Input: PE2 Input: PE3 LOW if PINMUX: PDOCON or PEOCON = 1 (bits [1:0]); otherwise No Change No Change No Change No Change No Change LOW if SCI is Enabled; otherwise No Change LOW if PINMUX: PDOCON = 1 (bit 1); otherwise, No Change STANDBY STATE No Change No Change No Change OUTPUT I/O NOTES DRIVE 12 mA 12 mA 12 mA I/O I/O I/O I/O I/O I/O 12 mA I/O I/O I/O I/O I/O I/O I/O 12 mA I/O I/O A6 B6 C6 H8 A5 B4 E7 B3 PF0/INT0 PF1/INT1 PF2/INT2 PF3/INT3 Input: PF0 Input: PF1 Input: PF2 Input: PF3 8 mA 8 mA 8 mA 8 mA I/O I/O I/O I/O 3 3 3 3 B5 C5 PF4/INT4/ SCVCCEN Input: PF4 8 mA I/O 3 D6 D6 PF5/INT5/ SCDETECT Input: PF5 No Change 8 mA I/O 3 E6 A4 PF6/INT6/ PCRDY1 Input: PF6 No Change 8 mA I/O 3 C5 A3 PF7/INT7/ PCRDY2 Input: PF7 No Change 8 mA I/O 3 R3 M6 PG0/nPCOE LOW: PG0 No Change 8 mA I/O T3 T1 PG1/nPCWE * GPIO Port G * Write Enable for PC Card (PCMCIA or CF) in sin- LOW: PG1 gle or dual card mode No Change 8 mA I/O Preliminary data sheet Rev. 01 -- 16 July 2007 9 LH7A400 NXP Semiconductors 32-Bit System-on-Chip Table 3. Functional Pin List (Cont'd) BGA PIN L6 LFBGA PIN P4 SIGNAL PG2/ nPCIOR PG3/ nPCIOW DESCRIPTION * GPIO Port G * I/O Read Strobe for PC Card (PCMCIA or CF) in single or dual card mode * GPIO Port G * I/O Write Strobe for PC Card (PCMCIA or CF) in single or dual card mode * GPIO Port G * Register Memory Access for PC Card (PCMCIA or CF) in single or dual card mode * GPIO Port G * Card Enable 1 for PC Card (PCMCIA or CF) in single or dual card mode. This signal and nPCCE2 are used by the PC Card for decoding low and high byte accesses. * GPIO Port G * Card Enable 2 for PC Card (PCMCIA or CF) in single or dual card mode. This signal and nPCCE1 are used by the PC Card for decoding low and high byte accesses. * GPIO Port G * Direction for PC Card (PCMCIA or CF) in single or dual card mode RESET STATE LOW: PG2 STANDBY STATE No Change OUTPUT I/O NOTES DRIVE 8 mA I/O M6 R3 LOW: PG3 No Change 8 mA I/O N6 T2 PG4/nPCREG LOW: PG4 No Change 8 mA I/O M7 P5 PG5/nPCCE1 LOW: PG5 No Change 8 mA I/O M8 R4 PG6/nPCCE2 LOW: PG6 No Change 8 mA I/O N4 T3 PG7/PCDIR LOW: PG7 No Change 8 mA I/O P4 P6 PH0/ PCRESET1 * GPIO Port H * Reset Card 1 for PC Card (PCMCIA or CF) in sin- Input: PH0 gle or dual card mode * GPIO Port H * Address Bit 8 for PC Card (CF) in single card mode Input: PH1 * Reset Card 2 for PC Card (PCMCIA or CF) in dual card mode * GPIO Port H * Enable Card 1 for PC Card (PCMCIA or CF) in sinInput: PH2 gle or dual card mode. This signal is used for gating other control signals to the appropriate PC Card. * GPIO Port H * Address Bit 9 for PC Card (CF) in single card mode * Address Bit 25 for PC Card (PCMCIA) in single card mode * Enable Card 2 for PC Card (PCMCIA or CF) in dual card mode. This signal is used for gating other control signals to the appropriate PC Card. * GPIO Port H * WAIT Signal for Card 1 for PC Card (PCMCIA or CF) in single or dual card mode * GPIO Port H * Address Bit 10 for PC Card (CF) in single card mode * Address Bit 24 for PC Card (PCMCIA) in single card mode * WAIT Signal for Card 2 for PC Card (PCMCIA or F) in dual card mode * GPIO Port H * Audio Codec (AC97) Reset * GPIO Port H * Status Read Enable for PC Card (PCMCIA or F) in single or dual card mode LCD Frame Synchronization pulse LCD Line Synchronization pulse No Change 8 mA I/O R4 T4 PH1/CFA8/ PCRESET2 No Change 8 mA I/O T4 M7 PH2/ nPCSLOTE1 No Change 8 mA I/O N7 T5 PH3/CFA9/ PCMCIAA25/ nPCSLOTE2 Input: PH3 No Change 8 mA I/O P8 R6 PH4/ nPCWAIT1 Input: PH4 No Change 8 mA I/O P5 R7 PH5/CFA10/ PCMCIAA24/ nPCWAIT2 Input: PH5 No Change 8 mA I/O R5 P7 PH6/ nAC97RESET PH7/ nPCSTATRE LCDFP LCDLP Input: PH6 No Change 8 mA I/O T5 R6 R8 T6 T7 R9 Input: PH7 LOW LOW No Change LOW LOW 8 mA 12 mA 12 mA I/O O O 10 Rev. 01 -- 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A400 Table 3. Functional Pin List (Cont'd) BGA PIN P9 N9 P7 R7 T7 N8 T15 T16 E7 D7 LFBGA PIN P9 N9 M8 P8 R8 T8 T16 R16 C7 A6 SIGNAL LCDENAB/ LCDM LCDDCLK LCDVD0 LCDVD1 LCDVD2 LCDVD3 USBDP USBDN nPWME0 nPWME1 USB Data Positive (Differential Pair) USB Data Negative (Differential Pair) * DC-DC Converter Pulse Width * Modulator 0 Enable * DC-DC Converter Pulse Width * Modulator 1 Enable * DC-DC Converter Pulse Width * Modulator 0 Output during normal operation and Polarity Selection input at reset * DC-DC Converter Pulse Width * Modulator 1 Output during normal operation and Polarity Selection input at reset * Audio Codec (AC97) Clock * Audio Codec (ACI) Clock * Audio Codec (AC97) Output * Audio Codec (ACI) Output * Audio Codec (AC97) Synchronization * Audio Codec (ACI) Synchronization * Audio Codec (AC97) Input * Audio Codec (ACI) Input * MultiMediaCard Clock (20 MHz MAX.) * MultiMediaCard SPI Mode Clock * MultiMediaCard Command * MultiMediaCard SPI Mode Data Input * MultiMediaCard Data * MultiMediaCard SPI Mode Data Output * UART2 Clear to Send Signal. This pin is an output for JTAG boundary scan only. * UART2 Data Carrier Detect Signal. This pin is output for JTAG boundary scan only. UART2 Data Set Ready Signal IrDA Transmit IrDA Receive. This pin is an output for JTAG boundary scan only. UART2 Transmit Data Output UART2 Receive Data Input. This pin is an output for JTAG boundary scan only. Synchronous Serial Port Clock Synchronous Serial Port Receive Synchronous Serial Port Transmit Synchronous Serial Port Frame Sync Input Input Input Input No Change No Change No Change No Change LCD Video Data Bus LOW LOW 12 mA DESCRIPTION LCD TFT Data Enable LCD STN AC Bias LCD Data Clock RESET STATE LOW: LCDENAB LOW STANDBY STATE LOW LOW OUTPUT I/O NOTES DRIVE 12 mA 12 mA O O O O O O I/O I/O I I 10 10 C7 B6 PWM0 Input No Change 8 mA I/O B7 B5 PWM1 Input No Change 8 mA I/O C4 D5 A2 A1 ACBITCLK ACOUT Input LOW No Change No Change 8 mA 8 mA I/O O B4 B2 ACSYNC LOW No Change 8 mA O A4 A3 B3 A2 E2 E3 E5 F2 F3 F4 J7 H4 J1 J2 J3 E6 C3 B1 D4 E1 F3 G4 G5 G6 F1 G3 J3 J6 J7 J2 ACIN MMCCLK/ MMSPICLK MMCCMD/ MMSPIDIN MMCDATA/ MMSPIDOUT UARTCTS2 UARTDCD2 UARTDSR2 UARTIRTX1 UARTIRRX1 UARTTX2 UARTRX2 SSPCLK SSPRX SSPTX SSPFRM/ nSSPFRM Input LOW: MMCCLK Input: MMCCMD Input: MMCDATA Input Input Input LOW Input HIGH Input LOW Input LOW Input No Change LOW Input Input No Change No Change No Change No Change No Change No Change No Change No Change No Change LOW Input 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA I O I/O I/O I I I O I O I O I I/O I/O Preliminary data sheet Rev. 01 -- 16 July 2007 11 LH7A400 NXP Semiconductors 32-Bit System-on-Chip Table 3. Functional Pin List (Cont'd) BGA PIN F6 F5 G1 G2 G4 G5 H1 H2 H3 C3 P11 R12 D1 D2 A1 B1 B2 C1 LFBGA PIN G2 G1 H3 H5 H6 H7 H2 H1 J1 F5 T14 T15 E3 F6 E5 C2 D3 C1 SIGNAL COL0 COL1 COL2 COL3 COL4 COL5 COL6 COL7 TBUZ MEDCHG WIDTH0 WIDTH1 BATOK nBATCHG TDI TCK TDO TMS Timer Buzzer (254 kHz MAX.) Boot Device Media Change. Used with WIDTH0 and WIDTH1 to specify boot memory device. External Memory Width Pins. Also, used with MEDCHG to specify the boot memory device size. The pins must be pulled HIGH with a 33 k resistor. Battery OK Battery Change JTAG Data In. This signal is internally pulled-up t o VDD. JTAG Clock. This signal should be externally pulled-up to VDD with a 33 k resistor. JTAG Data Out. This signal should be externally pulled up to VDD with a 33 k resistor. JTAG Test Mode select. This signal is internally pulled-up to VDD. Test Pin 0. Internally pulled up to VDD. For Normal mode, leave open. For JTAG mode, tie to GND. See Table 4. Test Pin 1. internally pulled up to VDD. For Normal and JTAG mode, leave open. See Table 4. LOW Input LOW No Change 8 mA O I 3 Keyboard Interface HIGH HIGH 8 mA O DESCRIPTION RESET STATE STANDBY STATE OUTPUT I/O NOTES DRIVE Input Input Input Input Input High-Z Input No Change No Change No Change No Change No Change No Change No Change 4 mA I I I I I O I 3 3 3 4 3 4 T12 P15 nTEST0 Input No Change I 4 R15 1. 2. 3. 4. 5. 6. 7. 8. 9. P13 nTEST1 Signals beginning with `n' are Active LOW. The SCLK pin can source up to 12 mA and sink up to 20 mA. See `DC Characteristics'. Schmitt trigger input; see 'DC Specifications', page 31 for triggers points and hysteresis. Input only for JTAG boundary scan mode. Output only for JTAG boundary scan mode. The internal pullup and pull-down resistance on all digital I/O pins is 50 k When used as SMBCLK, this pin must have a resistor. The RESET STATE is defined as the state during power-on reset. The STANDBY STATE is defined as the state when the device is in standby. During this state, I/O cells are forced to input (Input), output driving low (LOW), output driving high (HIGH), or their current state is preserved (No Change). In some case, function selection has an overall effect on the standby state. 10. All unused USB Device pins with a differential pair must be pulled to ground with a 15 k resistor. Table 4. nTest Pin Function MODE JTAG Normal nTEST0 0 1 nTEST1 1 1 nURESET 1 x 12 Rev. 01 -- 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A400 Table 5. LCD Data Multiplexing STN BGA PIN LFBGA PIN LCD DATA SIGNAL LCDVD17 LCDVD16 LCDVD15 LCDVD14 LCDVD13 LCDVD12 LCDVD11 LCDVD10 LCDVD9 LCDVD8 LCDVD7 LCDVD6 LCDVD5 LCDVD4 LCDVD3 LCDVD2 LCDVD1 LCDVD0 MUSTN3 MUSTN2 MUSTN1 MUSTN0 MLSTN3 MLSTN2 MLSTN1 MLSTN0 MUSTN3 MUSTN2 MUSTN1 MUSTN0 MUSTN7 MUSTN6 MUSTN5 MUSTN4 MUSTN3 MUSTN2 MUSTN1 MUSTN0 MLSTN7 MLSTN6 MLSTN5 MLSTN4 MLSTN3 MLSTN2 MLSTN1 MLSTN0 MUSTN7 MUSTN6 MUSTN5 MUSTN4 MUSTN3 MUSTN2 MUSTN1 MUSTN0 CUSTN7 CUSTN6 CUSTN5 CUSTN4 CUSTN3 CUSTN2 CUSTN1 CUSTN0 CLSTN7 CLSTN6 CLSTN5 CLSTN4 CLSTN3 CLSTN2 CLSTN1 CLSTN0 CUSTN7 CUSTN6 CUSTN5 CUSTN4 CUSTN3 CUSTN2 CUSTN1 CUSTN0 Intensity BLUE4 BLUE3 BLUE2 BLUE1 BLUE0 GREEN4 GREEN3 GREEN2 GREEN1 GREEN0 RED4 RED3 RED2 RED1 RED0 MONO 4-BIT SINGLE PANEL DUAL PANEL MONO 8-BIT SINGLE PANEL DUAL PANEL COLOR SINGLE PANEL DUAL PANEL TFT AD-TFT/ HR-TFT K1 J5 R10 P10 T9 R9 N11 K8 L11 M11 M10 M9 N10 L10 N8 T7 R7 P7 K2 K1 T13 R12 R11 T12 T11 P10 K10 M9 R10 T10 K9 T9 T8 R8 P8 M8 LOW LOW Intensity BLUE4 BLUE3 BLUE2 BLUE1 BLUE0 GREEN4 GREEN3 GREEN2 GREEN1 GREEN0 RED4 RED3 RED2 RED1 RED0 Notes: 1. The Intensity bit is identically generated for all three colors. 2. MU = Monochrome Upper 3. CU = Color Upper 4. CL = Color Lower Preliminary data sheet Rev. 01 -- 16 July 2007 13 LH7A400 NXP Semiconductors 32-Bit System-on-Chip Table 6. 256-Ball BGA Package Numerical Pin List BGA PIN A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 TDI MMCDATA/MMSPIDOUT MMCCLK/MMSPICLK ACIN VSS PF0/INT0 VDDC A27/SCRST DQM0 SCLK VSS nSCS3 A24 D24 A23 D23 TCK TDO MMCCMD/MMSPIDIN ACSYNC PF4/INT4/SCVCCEN PF1/INT1 PWM1 VDD DQM1 CS6/SCKE1_2 D30 D29 D25 VDD VSSC A22 TMS nEXTPWR MEDCHG ACBITCLK PF7/INT7/PCRDY2 PF2/INT2 PWM0 nWE0 VSSC CS7/SCKE0 nCAS nSWE D26 SIGNAL BGA PIN C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 Table 6. 256-Ball BGA Package Numerical Pin List (Cont'd) SIGNAL nSCS0 VSS A21 BATOK nBATCHG nPOR WAKEUP ACOUT PF5/INT5/SCDETECT nPWME1 nOE DQM2 nWE3 D31 VDDC nSCS1 D21 A20 D19 VDDC UARTCTS2 UARTDCD2 nPWRFL UARTDSR2 PF6/INT6/PCRDY1 nPWME0 VSS DQM3 VDD nSCS2 D27 A18 D18 VDDC A17/SB1 VDD UARTIRTX1 UARTIRRX1 UARTTX2 COL1 COL0 VSS A26/SCCLK nRAS D22 14 Rev. 01 -- 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A400 Table 6. 256-Ball BGA Package Numerical Pin List (Cont'd) BGA PIN F11 F12 F13 F14 F15 F16 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 J1 J2 J3 J4 J5 J6 J7 A19 D17 VDD A16/SB0 D16 A15/SA13 COL2 COL3 VSS COL4 COL5 VSSC VDD A25/SCIO SCKE3 D28 D14 D15 A14/SA12 A13/SA11 D13 A12/SA10 COL6 COL7 TBUZ SSPCLK VSSC nURESET VSS PF3/INT3 VSS D20 D6 VSSC D12 A11/SA9 D11 A10/SA8 SSPRX SSPTX SSPFRM/nSSPFRM VDDC PA0/LCDVD16 PGMCLK UARTRX2 SIGNAL BGA PIN J8 J9 J10 J11 J12 J13 J14 J15 J16 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 M1 M2 M3 Table 6. 256-Ball BGA Package Numerical Pin List (Cont'd) SIGNAL A6/SA4 A9/SA7 D10 VDD VDD D9 A8/SA6 D8 A7/SA5 PA1/LCDVD17 PA2 PA3 VSS PA4 PC3/LCDREV VDD PD2/LCDVD10 VDDC nCS1 nCS0 D7 VSS A5/SA3 A4/SA2 A3/SA1 PA5 PA6 PA7 PB0/UARTRX1 PB1/UARTTX3 PG2/nPCIOR PB2/UARTRX3 PC4/LCDSPS VSSC PE0/LCDVD4 PD1/LCDVD9 D0 VDDC D5 D4 D3 VDD PB3/UARTCTS3 VSSC Preliminary data sheet Rev. 01 -- 16 July 2007 15 LH7A400 NXP Semiconductors 32-Bit System-on-Chip Table 6. 256-Ball BGA Package Numerical Pin List (Cont'd) BGA PIN M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 PB4/UARTDCD3 VDD PG3/nPCIOW PG5/nPCCE1 PG6/nPCCE2 PE2/LCDVD6 PE3/LCDVD7 PD0/LCDVD8 nCS3/nMMSPICS A2/SA0 VDD D1 A0/nWE1 PB5/UARTDSR3 PB6/SWID/SMBD PB7/SMBCLK PG7/PCDIR VSS PG4/nPCREG PH3/CFA9/PCMCIAA25/nPCSLOTE2 LCDVD3 LCDDCLK PE1/LCDVD5 PD3/LCDVD11 VDDA D2 A1/nWE2 VSSC VSS PC0/UARTTX1 PC1/LCDPS VDDC PH0/PCRESET1 PH5/CFA10/PCMCIAA24/nPCWAIT2 VSS LCDVD0 PH4/nPCWAIT1 LCDENAB/LCDM PD6/LCDVD14 WIDTH0 VSSA nCS2 CLKEN XTAL32OUT SIGNAL BGA PIN P16 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 Table 6. 256-Ball BGA Package Numerical Pin List (Cont'd) SIGNAL XTAL32IN PC2/LCDVDDEN PC7/LCDSPL PG0/nPCOE PH1/CFA8/PCRESET2 PH6/nAC97RESET LCDFP LCDVD1 LCDLP PD4/LCDVD12 PD7/LCDVD15 VDDA WIDTH1 XTALIN VDD nTEST1 VSS PC5/LCDCLS PC6/LCDHRLP PG1/nPCWE PH2/nPCSLOTE1 PH7/nPCSTATRE VDD LCDVD2 VDDC PD5/LCDVD13 VSSC VSSA nTEST0 XTALOUT VSS USBDP USBDN 16 Rev. 01 -- 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A400 Table 7. 256-Ball LFBGA Package Numerical Pin List LFBGA PIN A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 ACOUT ACBITCLK PF7/INT7/PCRDY2 PF6/INT6/PCRDY1 PF0/INT0 nPWME1 A27/SCRST DQM3 DQM1 CS7/SCKE0 SCKE3 D31 nSWE D29 nSCS1 D25 MMCCMD/MMSPIDIN ACSYNC PF3/INT3 PF1/INT1 PWM1 PWM0 A26/SCCLK VSS DQM2 SCLK nCAS D30 D26 D27 A23 D23 TMS TCK MMCCLK/MMSPICLK VDDC PF4/INT4/SCVCCEN VSS nPWME0 nOE DQM0 VDD nRAS D28 nSCS0 SIGNAL Table 7. 256-Ball LFBGA Package Numerical Pin List LFBGA PIN C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 F1 F2 F3 F4 F5 F6 F7 F8 F9 A22 A21 A20 nURESET nEXTPWR TDO MMCDATA/MMSPIDOUT VSS PF5/INT5/SCDETECT VDDC A25/SCIO nWE3 VDDC nSCS2 D24 VSS D21 A19 D18 UARTCTS2 WAKEUP BATOK nPOR TDI ACIN PF2/INT2 VSS CS6/SCKE1_2 nSCS3 A24 D22 D20 A18 D17 A16/SB0 UARTTX2 nPWRFL UARTDCD2 VDDC MEDCHG nBATCHG VSS nWE0 VDD SIGNAL Preliminary data sheet Rev. 01 -- 16 July 2007 17 LH7A400 NXP Semiconductors 32-Bit System-on-Chip Table 7. 256-Ball LFBGA Package Numerical Pin List LFBGA PIN F10 F11 F12 F13 F14 F15 F16 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 J1 J2 J3 J4 J5 VDDC VDD D19 A17/SB1 VDD D16 A15/SA13 COL1 COL0 UARTRX2 UARTDSR2 UARTIRTX1 UARTIRRX1 VSSC VDD D13 A13/SA11 A14/SA12 D15 VSS D14 A12/SA10 D12 COL7 COL6 COL2 VSSC COL3 COL4 COL5 VSSC VSS A10/SA8 D11 A11/SA9 VDD D10 A9/SA7 D9 TBUZ SSPFRM/nSSPFRM SSPCLK VDDC PGMCLK SIGNAL Table 7. 256-Ball LFBGA Package Numerical Pin List LFBGA PIN J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 M1 SSPRX SSPTX VDDC VDD D8 A7/SA5 D7 A6/SA4 VSS D6 A8/SA6 PA0/LCDVD16 PA1/LCDVD17 PA2 PA3 PA5 PA4 VSS VDDC PE1/LCDVD5 PD1/LCDVD9 D3 A3/SA1 A4/SA2 D5 VDD A5/SA3 PA6 PA7 PB0/UARTRX1 VSSC PB4/UARTDCD3 VDDC VDD VSS VSSC VSS D0 VSS D1 D2 A2/SA0 D4 PB1/UARTTX3 SIGNAL 18 Rev. 01 -- 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A400 Table 7. 256-Ball LFBGA Package Numerical Pin List LFBGA PIN M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 PB2/UARTRX3 PB3/UARTCTS3 PB7/SMBCLK PC3/LCDREV PG0/nPCOE PH2/nPCSLOTE1 LCDVD0 PD0/LCDVD8 VDDA VSS CLKEN XTAL32OUT VSS A0/nWE1 A1/nWE2 PB5/UARTDSR3 PB6/SWID/SMBD VSSC PC5/LCDCLS PC7/LCDSPL VDD VSSC VDD LCDDCLK VSSC VSSA VDD VDD XTAL32IN nCS2 nCS3/nMMSPICS PC0/UARTTX1 PC1/LCDPS PC4/LCDSPS PG2/nPCIOR PG5/nPCCE1 PH0/PCRESET1 PH6/AC97RESET LCDVD1 LCDENAB/LCDM PD2/LCDVD10 VDD VDDA nTEST1 SIGNAL Table 7. 256-Ball LFBGA Package Numerical Pin List LFBGA PIN P14 P15 P16 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 nCS0 nTEST0 nCS1 PC2/LCDVDDEN PC6/LCDHRLP PG3/nPCIOW PG6/nPCCE2 VSSC PH4/nPCWAIT1 PH5/CFA10/PCMCIAA24/nPCWAIT2 LCDVD2 LCDLP PE3/LCDVD7 PD5/LCDVD13 PD6/LCDVD14 VSSA XTALIN XTALOUT USBDN PG1/nPCWE PG4/nPCREG PG7/PCDIR PH1/CFA8/PCRESET2 PH3/CFA9/PCMCIAA25/nPCSLOTE2 PH7/nPCSTATRE LCDFP LCDVD3 PE0/LCDVD4 PE2/LCDVD6 PD3/LCDVD11 PD4/LCDVD12 PD7/LCDVD15 WIDTH0 WIDTH1 USBDP SIGNAL Preliminary data sheet Rev. 01 -- 16 July 2007 19 LH7A400 NXP Semiconductors 32-Bit System-on-Chip TOUCH SCREEN CONTR. ROM FLASH 1 4 7 2 5 8 0 3 6 9 # * SMART CARD STN/TFT/ AD-TFT SSP UART SCI MULTIMEDIA CARD SRAM GPIO MMC SDRAM LH7A400 COMPACT FLASH DMA CODEC AC97 PC CARD PCMCIA UART USB IR BMI DC to DC VOLTAGE GENERATION CIRCUITRY BATTERY LH7A400-3 Figure 4. Application Diagram SYSTEM DESCRIPTIONS ARM922T Processor The LH7A400 microcontroller features the ARM922T cached core with an Advanced High Performance Bus (AHB) interface. The processor is a member of the ARM9T family of processors. For more information, see the ARM document, `ARM922T Technical Reference Manual', available on ARM's website at www.arm.com. The 32.768 kHz clock provides the source for the Real Time Clock tree and power-down logic.This clock is used for the power state control in the design and is the only clock in the LH7A400 that runs permanently. The 32.768 kHz clock is divided down to 1 Hz using a ripple divider to save power. This generated 1 Hz clock is used in the Real Time Clock counter. The 14.7456 MHz source is used to generate the main system clocks for the LH7A400. It is the source for PLL1 and PLL2, it acts as the primary clock to the peripherals and is the source clock to the Programmable clock (PGM) divider. PLL1 provides the main clock tree for the chip, it generates the following clocks: FCLK, HCLK and PCLK. FCLK is the clock that drives the ARM922T core. HCLK is the main bus (AHB) clock, as such it clocks all memory interfaces, bus arbitrators and the AHB peripherals. HCLK is generated by dividing FCLK by 1, 2, 3, or 4. HCLK can be gated by the system to enable low power operation. PCLK is the peripheral bus (APB) clock. It is generated by dividing HCLK by either 2, 4, or 8. PLL2 is used to generate a fixed frequency of 48 MHz for the USB peripheral. Clock and State Controller The clocking scheme in the LH7A400 is based around two primary oscillator inputs. These are the 14.7456 MHz input crystal and the 32.768 kHz real time clock oscillator. See Figure 5. The 14.7456 MHz oscillator is used to generate the main system clock domains for the LH7A400, where as the 32.768 kHz is used for controlling the power down operations and real time clock peripheral. The clock and state controller provides the clock gating and frequency division necessary, and then supplies the clocks to the processor and to the rest of the system. The amount of clock gating that actually takes place is dependent on the current power saving mode selected. 20 Rev. 01 -- 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A400 14.7456 MHz MAIN OSC. 32.768 kHz RTC OSC. FCLK STATE CONTROLLER HCLK (TO PROCESSOR CORE) DIVIDE REGISTER HCLK /2, /4, /8 PCLKs LH7A400-4 Figure 5. Clock and State Controller Block Diagram Power Modes The LH7A400 has three operational states: Run, Halt, and Standby. In Run mode, all clocks are hardware-enabled and the processor is clocked. Halt mode stops the processor clock while waiting for an event such as a key press, but the device continues to function. Finally, Standby equates to the computer being switched `off', i.e. no display (LCD disabled) and the main oscillator is shut down. The 32.768 kHz oscillator operates in all three modes. Data Paths The data paths in the LH7A400 are: * The AMBA AHB bus * The AMBA APB bus * The External Bus Interface * The LCD AHB bus * The DMA busses. AMBA AHB BUS The Advanced Microprocessor Bus Architecture Advanced High-performance Bus (AMBA AHB) bus is a high speed 32-bit-wide data bus. The AMBA AHB is for high-performance, high clock frequency system modules. Peripherals that have high bandwidth requirements are connected to the LH7A400 core processor using the AHB bus. These include the external and internal memory interfaces, the LCD registers, palette RAM and the bridge to the Advanced Peripheral Bus (APB) interface. The APB Bridge transparently converts the AHB access into the slower speed APB accesses. All of the control registers for the APB peripherals are programmed using the AHB - APB bridge interface. The main AHB data and address lines are configured using a multiplexed bus. This removes the need for tri-state buffers and bus holders, and simplifies bus arbitration. Reset Modes There are three external signals that can generate resets to the LH7A400; these are nPOR (power on reset), nPWRFL (power failure) and nURESET (user reset). If any of these are active, a system reset is generated internally. A nPOR reset performs a full system reset. The nPWRFL and nURESET resets will perform a full system reset except for the SDRAM refresh control, SDRAM Global Configuration, SDRAM Device Configuration and the RTC peripheral registers. The SDRAM controller will issue a self-refresh command to external SDRAM before the system enters this reset (the nPWRFL and nURESET resets only, not so for the nPOR reset). This allows the system to maintain its Real Time Clock and SDRAM contents. On coming out of reset, the chip enters Standby mode. Once in Run mode the PWRSR register can be interrogated to determine the nature of the reset, and the trigger source, after which software can then take appropriate actions. Preliminary data sheet Rev. 01 -- 16 July 2007 21 LH7A400 NXP Semiconductors 32-Bit System-on-Chip AMBA APB BUS The AMBA APB bus is a lower-speed 32-bit-wide peripheral data bus. The speed of this bus is selectable to be a divide-by-2, divide-by-4 or divide-by-8 of the speed of the AHB bus. EXTERNAL BUS INTERFACE The External Bus Interface (EBI) provides a 32-bit wide, high speed gateway to external memory devices. The memory devices supported include: * Asynchronous RAM/ROM/Flash * Synchronous DRAM/Flash * PCMCIA interfaces * CompactFlash interfaces. The EBI can be controlled by either the Asynchronous memory controller or Synchronous memory controller. There is an arbiter on the EBI input, with priority given to the Synchronous Memory Controller interface. LCD AHB BUS The LCD controller has its own local memory bus that connects it to the system's embedded memory and external SDRAM. The function of this local data bus is to allow the LCD controller to perform its video refresh function without congesting the AHB bus. This leads to better system performance and lower power consumption. There is an arbiter on both the embedded memory and the synchronous memory controller. In both cases the LCD bus is given priority. DMA BUSES The LH7A400 has a DMA system that connects the higher speed/higher data volume APB peripherals (MMC, USB and AC97) to the AHB bus. This enables the efficient transfer of data between these peripherals and external memory without the intervention of the ARM922T core. The DMA engine does not support memory to memory transfers. The LH7A400 can boot from either synchronous or asynchronous ROM/Flash. The selection is determined by the value of the MEDCHG pin at Power On Reset as shown in Table 8. When booting from synchronous memory, then synchronous bank 4 (nSCS3) is mapped into memory location zero. When booting from asynchronous memory, asynchronous memory bank 0 (nSCS0) is mapped into memory location zero. Figure 6 shows the memory map of the LH7A400 system for the two boot modes. Once the LH7A400 has booted, the boot code can configure the ARM922T MMU to remap the low memory space to a location in RAM. This allows the user to set the interrupt vector table. Table 8. Boot Modes BOOT MODE 8-bit ROM 16-bit ROM 32-bit ROM 32-bit ROM 16-bit SFlash (Initializes Mode Register) 16-bit SROM (Initializes Mode Register) 32-bit SFlash (Initializes Mode Register) 32-bit SROM (Initializes Mode Register) LATCHED BOOTWIDTH1 0 0 1 1 0 0 1 1 LATCHED BOOTWIDTH0 0 1 0 1 0 1 0 1 LATCHED MEDCHG 0 0 0 0 1 1 1 1 Interrupt Controller The LH7A400 interrupt controller is designed to control the interrupts from 28 different sources. Four interrupt sources are mapped to the FIQ input of the ARM922T and 24 are mapped to the IRQ input. FIQs have a higher priority than the IRQs. If two interrupts with the same priority become active at the same time, the priority must be resolved in software. When an interrupt becomes active, the interrupt controller generates an FIQ or IRQ if the corresponding mask bit is set. No latching of interrupts takes place in the controller. After a Power On Reset all mask register bits are cleared, therefore masking all interrupts. Hence, enabling of the mask register must be done by software after a power-on-reset. Memory Map The LH7A400 system has a 32-bit-wide address bus. This allows it to address up to 4GB of memory. This memory space is subdivided into a number of memory banks; see Figure 6. Four of these banks (each of 256MB) are allocated to the Synchronous memory controller. Eight of the banks (again, each 256MB) are allocated to the Asynchronous memory controller. Two of these eight banks are designed for PCMCIA systems. Part of the remaining memory space is allocated to the embedded SRAM, and to the control registers of the AHB and APB. The rest is unused. 22 Rev. 01 -- 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A400 F000.0000 E000.0000 D000.0000 C000.0000 B001.4000 B000.0000 8000.3800 8000.2000 8000.0000 7000.0000 6000.0000 5000.0000 4000.0000 3000.0000 2000.0000 1000.0000 0000.0000 ASYNCHRONOUS MEMORY (nCS0) SYNCHRONOUS MEMORY (nSCS2) SYNCHRONOUS MEMORY (nSCS1) SYNCHRONOUS MEMORY (nSCS0) RESERVED EMBEDDED SRAM RESERVED AHB INTERNAL REGISTERS APB INTERNAL REGISTERS ASYNCHRONOUS MEMORY (CS7) ASYNCHRONOUS MEMORY (CS6) PCMCIA/CompactFlash (nPCSLOTE2) PCMCIA/CompactFlash (nPCSLOTE1) ASYNCHRONOUS MEMORY (nCS3) ASYNCHRONOUS MEMORY (nCS2) ASYNCHRONOUS MEMORY (nCS1) SYNCHRONOUS ROM (nSCS3) SYNCHRONOUS MEMORY BOOT SYNCHRONOUS MEMORY (nSCS3) SYNCHRONOUS MEMORY (nSCS2) SYNCHRONOUS MEMORY (nSCS1) SYNCHRONOUS MEMORY (nSCS0) RESERVED EMBEDDED SRAM RESERVED AHB INTERNAL REGISTERS APB INTERNAL REGISTERS ASYNCHRONOUS MEMORY (CS7) ASYNCHRONOUS MEMORY (CS6) PCMCIA/CompactFlash (nPCSLOTE2) PCMCIA/CompactFlash (nPCSLOTE1) ASYNCHRONOUS MEMORY (nCS3) ASYNCHRONOUS MEMORY (nCS2) ASYNCHRONOUS MEMORY (nCS1) ASYNCHRONOUS ROM (nCS0) ASYNCHRONOUS MEMORY BOOT 256MB 256MB 256MB 256MB 80KB 256MB 256MB 256MB 256MB 256MB 256MB 256MB 256MB LH7A400-6 Figure 6. Memory Mapping for Each Boot Mode External Bus Interface The external bus interface allows the ARM922T, LCD controller and DMA engine access to an external memory system. The LCD controller has access to an internal frame buffer in embedded SRAM and an extension buffer in Synchronous Memory for large displays. The processor and DMA engine share the main system bus, providing access to all external memory devices and the embedded SRAM frame buffer. An arbitration unit ensures that control over the External Bus Interface (EBI) is only granted when an existing access has been completed. See Figure 7. 4 kB page boundary in SDRAM, allowing software to set the MMU (in the LCD controller) page tables such that the two memory areas appear contiguous. Byte, Half-Word and Word accesses are permissible. Asynchronous Memory Controller The Asynchronous memory controller is incorporated as part of the memory controller to provide an interface between the AMBA AHB system bus and external (off-chip) memory devices. The Asynchronous Memory Controller provides support for up to eight independently configurable memory banks simultaneously. Each memory bank is capable of supporting: * SRAM * ROM * Flash EPROM * Burst ROM memory. Each memory bank may use devices using either 8-, 16-, or 32-bit external memory data paths. The memory controller supports only little-endian operation. The memory banks can be configured to support: * Non-burst read and write accesses only to highspeed CMOS static RAM. * Non-burst write accesses, nonburst read accesses and asynchronous page mode read accesses to fast-boot block flash memory. Embedded SRAM The amount of Embedded SRAM contained in the LH7A400 is 80 kB. This Embedded memory is designed to be used for storing code, data, or LCD frame data and to be contiguous with external SDRAM. The 80 kB is large enough to store a QVGA panel (320 x 240) at 8 bits per pixel, equivalent to 70 kB of information. Containing the frame buffer on chip reduces the overall power consumed in any application that uses the LH7A400. Normally, the system has to perform external accesses to acquire this data. The LCD controller is designed to automatically use an overflow frame buffer in SDRAM if a larger screen size is required. This overflow buffer can be located on any Preliminary data sheet Rev. 01 -- 16 July 2007 23 LH7A400 NXP Semiconductors 32-Bit System-on-Chip EXTERNAL TO THE LH7A400 INTERNAL TO THE LH7A400 ARM922T SDRAM SRAM EXTERNAL BUS INTERFACE ADDRESS (EBI) and CONTROL DATA ARBITER PCMCIA/CF SUPPORT SYNCHRONOUS DYNAMIC MEMORY CONTROLLER (SDMC) ARBITER SDRAM ROM 80KB EMBEDDED SRAM LCD AHB LCD MEMORY MANAGEMENT UNIT (MMU) COLOR LCD CONTROLLER (CLCDC) DMA CONTROLLER AD-TFT LCD TIMING CONTROLLER ADVANCED HIGH-PERFORMANCE BUS (AHB) LH7A400-8 Figure 7. External Bus Interface Block Diagram 24 Rev. 01 -- 16 July 2007 ARBITER ARBITER ASYNCHRONOUS STATIC MEMORY CONTROLLER (SMC) Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A400 The Asynchronous Memory Controller has six main functions: * * * * * * Memory bank select Access sequencing Wait states generation Byte lane write control External bus interface CompactFlash or PCMCIA interfacing. MMC bus lines can be divided into three groups: * Power supply: VDD and VSS * Data Transfer: MMCCMD, MMCDATA * Clock: MMCLK. MULTIMEDIACARD ADAPTER The MultiMediaCard Adapter implements MultiMediaCard specific functions, serves as the bus master for the MultiMediacard Bus and implements the standard interface to the MultiMediaCard Cards (card initialization, CRC generation and validation, command/response transactions, etc.). Synchronous Memory Controller The Synchronous memory controller provides a high speed memory interface to a wide variety of Synchronous memory devices, including SDRAM, Synchronous Flash and Synchronous ROMs. The key features of the controller are: * LCD DMA port for high bandwidth * Up to four Synchronous Memory banks that can be independently set up * Special configuration bits for Synchronous ROM operation * Ability to program Synchronous Flash devices using write and erase commands * On booting from Synchronous ROM, (and optionally with Synchronous Flash), a configuration sequence is performed before releasing the processor from reset * Data is transferred between the controller and the SDRAM in quad-word bursts. Longer transfers within the same page are concatenated, forming a seamless burst * Programmable for 16- or 32-bit data bus size * Two reset domains are provided to enable SDRAM contents to be preserved over a `soft' reset * Power saving Synchronous Memory SCKE and external clock modes provided. Smart Card Interface (SCI) The SCI (ISO7816) interfaces to an external Smart Card reader. The SCI can autonomously control data transfer to and from the smart card. Transmit and receive data FIFOs are provided to reduce the required interaction between the CPU core and the peripheral. SCI FEATURES * Supports asynchronous T0 and T1 transmission protocols * Supports clock rate conversion factor F = 372, with bit rate adjustment factors D = 1, 2, or 4 supported * Eight-character-deep buffered Tx and Rx paths * Direct interrupts for Tx and Rx FIFO level monitoring * Interrupt status register * Hardware-initiated card deactivation sequence on detection of card removal * Software-initiated card deactivation sequence on transaction complete * Limited support for synchronous Smart Cards via registered input/output. PROGRAMMABLE PARAMETERS * Smart Card clock frequency * Communication baud rate * Protocol convention * Card activation/deactivation time * Check for maximum time for first character of Answer to Reset - ATR reception * Check for maximum duration of ATR character stream * Check for maximum time of receipt of first character of data stream * Check for maximum time allowed between characters * Character guard time * Block guard time * Transmit/receive character retry. MultiMediaCard (MMC) The MMC adapter combines all of the requirements and functions of an MMC host. The adapter supports the full MMC bus protocol, defined by the MMC Definition Group's specification v.2.11. The controller can also implement the SPI interface to the cards. INTERFACE DESCRIPTION AND MMC OVERVIEW The MMC controller uses the three-wire serial data bus (clock, command, and data) to transfer data to and from the MMC card, and to configure and acquire status information from the card's registers. Preliminary data sheet Rev. 01 -- 16 July 2007 25 LH7A400 NXP Semiconductors 32-Bit System-on-Chip Direct Memory Access Controller (DMA) The DMA Controller interfaces streams from the following three peripherals to the system memory: * USB (1 Tx and 1 Rx DMA Channel) * MMC (1 Tx and 1 Rx DMA Channel) * AC97 (3 Tx and 3 Rx DMA Channels). Each has its own bi-directional peripheral DMA bus capable of transferring data in both directions simultaneously. All memory transfers take place via the main system AHB bus. DMA Specific features are: * Independent DMA channels for Tx and Rx * Two Buffer Descriptors per channel to avoid potential data under/over-flows due to software introduced latency * No Buffer wrapping * Buffer size may be equal to, greater than, or less than the packet size. Transfers can automatically switch between buffers. * Maskable interrupt generation * Internal arbitration between DMA Channels and external bus arbiter. * For DMA Data transfer sizes, byte, word and quadword data transfers are supported. A set of control and status registers are available to the system processor for setting up DMA operations and monitoring their status. A system interrupt is generated when any or all of the DMA channels wish to inform the processor that a new buffer needs to be allocated. The DMA controller services three peripherals using ten DMA channels, each with its own peripheral DMA bus capable of transferring data in both directions simultaneously. The MMC and USB peripherals each use two DMA channels, one for transmit and one for receive. The AC97 peripheral uses six DMA channels (three transmit and three receive) to allow different sample frequency data queues to be handled with low software overheads. The DMA Controller does not support memory to memory transfers. Color LCD Controller The LH7A400's LCD Controller is programmable to support up to 1,024 x 768, 16-bit color LCD panels. It interfaces directly to STN, color STN, TFT, AD-TFT, and HR-TFT panels. Unlike other LCD controllers, the LH7A400's LCD Controller incorporates the timing conversion logic from TFT to HR- and AD-TFT, allowing a direct interface to these panels and minimizing external chip count. The Color LCD Controller features support for: * Up to 1,024 x 768 Resolution * 16-bit Video Bus * STN, Color STN, AD-TFT, HR-TFT, TFT panels * Single and Dual Scan STN panels * Up to 15 Gray Shades * Up to 64,000 Colors AC97 Advanced Audio Codec Interface The AC97 Advanced Audio Codec controller includes a 5-pin serial interface to an external audio codec. The AC97 LINK is a bi-directional, fixed rate, serial Pulse Code Modulation (PCM) digital stream, dividing each audio frame into 12 outgoing and 12 incoming data streams (slots), each with 20-bit sample resolution. The AC97 controller contains logic that controls the AC97 link to the Audio Codec and an interface to the AMBA APB. Its main features include: * Serial-to-parallel conversion for data received from the external codec * Parallel-to-serial conversion for data transmitted to the external codec * Reception/Transmission of control and status information via the AMBA APB interface * Supports up to 4 different codec sampling rates at a time with its 4 transmit and 4 receive channels. The transmit and receive paths are buffered with internal FIFO memories, allowing data to be stored independently in both transmit and receive modes. The outgoing data for the FIFOs can be written via either the APB interface or with DMA channels 1 - 3. USB Device The features of the USB are: * Fully compliant to USB 1.1 specification * Provides a high level interface that shields the firmware from USB protocol details * Compatible with both OpenHCI and Intel's UHCI standards * Supports full-speed (12 Mbps) functions * Supports Suspend and Resume signalling. 26 Rev. 01 -- 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A400 Audio Codec Interface (ACI) The ACI provides: * A digital serial interface to an off-chip 8-bit CODEC * All the necessary clocks and timing pulses to perform serialization or de-serialization of the data stream to or from the CODEC device. The interface supports full duplex operation and the transmit and receive paths are buffered with internal FIFO memories allowing up to 16 bytes to be stored independently in both transmit and receive modes. The ACI includes a programmable frequency divider that generates a common transmit and receive bit clock output from the on-chip ACI clock input (ACICLK). Transmit data values are output synchronous with the rising edge of the bit clock output. Receive data values are sampled on the falling edge of the bit clock output. The start of a data frame is indicated by a synchronization output signal that is synchronous with the bit clock. The transmit and receive paths are buffered with internal FIFO memories allowing up to 16 bytes to be stored independently in both transmit and receive modes. The UART can generate: * Four individually maskable interrupts from the receive, transmit and modem status logic blocks * A single combined interrupt so that the output is asserted if any of the individual interrupts are asserted and unmasked. If a framing, parity, or break error occurs during reception, the appropriate error bit is set, and is stored in the FIFO. If an overrun condition occurs, the overrun register bit is set immediately and the FIFO data is prevented from being overwritten. UART1 also supports IrDA 1.0 (15.2 kbit/s). The modem status input signals Clear to Send (CTS), Data Carrier Detect (DCD) and Data Set Ready (DSR) are supported on UART2 and UART3. Synchronous Serial Port (SSP) The LH7A400 SSP is a master-only interface for synchronous serial communication with device peripheral devices that has either Motorola SPI, National Semiconductor MICROWIRE or Texas Instruments Synchronous Serial Interfaces. The LH7A400 SSP performs serial-to-parallel conversion on data received from a peripheral device. The transmit and receive paths are buffered with internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit and receive modes. Serial data is transmitted on SSPTXD and received on SSPRXD. The LH7A400 SSP includes a programmable bit rate clock divider and prescaler to generate the serial output clock SCLK from the input clock SSPCLK. Bit rates are supported to 2 MHz and beyond, subject to choice of frequency for SSPCLK; the maximum bit rate will usually be determined by peripheral devices. Timers Two identical timers are integrated in the LH7A400. Each of these timers has an associated 16-bit read/write data register and a control register. Each timer is loaded with the value written to the data register immediately, this value will then be decremented on the next active clock edge to arrive after the write. When the timer underflows, it will immediately assert its appropriate interrupt. The timers can be read at any time. The clock source and mode is selectable by writing to various bits in the system control register. Clock sources are 508 kHz and 2 kHz. Timer 3 (TC3) has the same basic operation, but is clocked from a single 7.3728 MHz source. It has the same register arrangement as Timer 1 and Timer 2, providing a load, value, control and clear register. Once the timer has been enabled and is written to, unlike the Timer 1 and Timer 2, will decrement the timer on the next rising edge of the 7.3728 MHz clock after the data register has been updated. All the timers can operate in two modes, free running mode or pre-scale mode. FREE-RUNNING MODE In free-running mode, the timer will wrap around to 0xFFFF when it underflows and continue counting down. PRE-SCALE MODE In pre-scale (periodic) mode, the value written to each timer is automatically re-loaded when the timer underflows. This mode can be used to produce a programmable frequency to drive an external buzzer or generate a periodic interrupt. UART/IrDA The LH7A400 contains three UARTs, UART1, UART2, and UART3. The UART performs: * Serial-to-Parallel conversion on data received from the peripheral device * Parallel-to-Serial conversion on data transmitted to the peripheral device. Preliminary data sheet Rev. 01 -- 16 July 2007 27 LH7A400 NXP Semiconductors 32-Bit System-on-Chip Real Time Clock (RTC) The RTC can be used to provide a basic alarm function or long time-base counter. This is achieved by generating an interrupt signal after counting for a programmed number of cycles of a real-time clock input. Counting in one second intervals is achieved by use of a 1 Hz clock input to the RTC. DC-to-DC Converter The features of the DC-DC Converter interface are: * Dual drive PWM outputs, with independent closed loop feedback * Software programmable configuration of one of 8 output frequencies (each being a fixed divide of the input clock). * Software programmable configuration of duty cycle from 0 to 15/16, in intervals of 1/16. * Output polarity (for positive or negative voltage generation) is hardware-configured during power-on reset via the polarity select inputs * Each PWM output can be dynamically switched to one of a pair of preprogrammed frequency/duty cycle combinations via external pins. Battery Monitor Interface (BMI) The LH7A400 BMI is a serial communication interface specified for two types of Battery Monitors/Gas Gauges. The first type employs a single wire interface. The second interface employs a two-wire multi-master bus, the Smart Battery System Specification. If both interfaces are enabled at the same time, the Single Wire Interface will have priority. A brief overview of these two interface types are given here. SINGLE WIRE INTERFACE The Single Wire Interface performs: * Serial-to-parallel conversion on data received from the peripheral device * Parallel-to-serial conversion on data transmitted to the peripheral device * Data packet coding/decoding on data transfers (incorporating Start/Data/Stop data packets) The Single Wire interface uses a command-based protocol, in which the host initiates a data transfer by sending a WriteData/Command word to the Battery Monitor. This word will always contain the Command section, which tells the Single Wire Interface device the location for the current transaction. The most significant bit of the Command determines if the transaction is Read or Write. In the case of a Write transaction, then the word will also contain a WriteData section with the data to be written to the peripheral. SMART BATTERY INTERFACE The SMBus Interface performs: * Serial-to-Parallel conversion on data received from the peripheral device * Parallel-to-Serial conversion of data transmitted to the peripheral device. The Smart Battery Interface uses a two-wire multimaster bus (the SMBus), meaning that more than one device capable of controlling the bus can be connected to it. A master device initiates a bus transfer and provides the clock signals. A slave device can receive data provided by the master or it can provide data to the master. Since more than one device may attempt to take control of the bus as a master, SMBus provides an arbitration mechanism, by relying on the wired-AND connection of all SMBus interfaces to the SMBus. Watchdog Timer (WDT) The Watchdog Timer provides hardware protection against malfunctions. It is a programmable timer that is reset by software at regular intervals. Failure to reset the timer will cause a FIQ interrupt. Failure to service the FIQ interrupt will then generate a System Reset. The WDT features are: * Driven by the system clock * 16 programmable time-out periods: 216 through 231 clock cycles * Generates a system reset (resets LH7A400) or a FIQ Interrupt whenever a time-out period is reached * Software enable, lockout, and counter-reset mechanisms add security against inadvertent writes * Protection mechanism guards against interrupt-service-failure: - The first WDT time-out triggers FIQ and asserts nWDFIQ status flag - If FIQ service routine fails to clear nWDFIQ, then the next WDT time-out triggers a System Reset. General Purpose I/O (GPIO) The LH7A400 GPIO has eight ports, each with a data register and a data direction register. It also has added registers including Keyboard Scan, PINMUX, GPIO Interrupt Enable, INTYPE1/2, GPIOFEOI, and PGHCON. The data direction register determines whether a port is configured as an input or an output while the data register is used to read the value of the GPIO pins. The GPIO Interrupt Enable, INTYPE1/2, and GPIOFEOI registers are used to control edge-triggered Interrupts on Port F. The PINMUX register controls what signals are output of Port D and Port E when they are set as outputs, while the PGHCON controls the operations of Port G and H. 28 Rev. 01 -- 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A400 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings PARAMETER DC Core Supply Voltage (VDDC) DC I/O Supply Voltage (VDD) DC Analog Supply Voltage (VDDA) 5 V Tolerant Digital Input Pin Voltage ESD, Human Body Model (Analog pins AN0 - AN9 rated at 500 V) ESD, Charged Device Model Storage Temperature NOTE: Except for Storage Temperature, these ratings are only for transient conditions. Operation at or beyond absolute maximum rating conditions may affect reliability and cause permanent damage to the device. MINIMUM -0.3 V -0.3 V -0.3 V -0.5 V MAXIMUM 2.4 V 4.6 V 2.4 V 5.5 V 2 kV 1 kV -55C 125C Recommended Operating Conditions PARAMETER DC Core Supply Voltage (VDDC) DC Core Supply Voltage (VDDC) DC I/O Supply Voltage (VDD) DC I/O Supply Voltage (VDD) DC Analog Supply Voltage for PLLs (VDDA) Clock Frequency (0C to +70C) Clock Frequency (-40C to +85C) Bus Clock Frequency (-40C to +85C) Clock Frequency (0C to +70C) Clock Frequency (-40C to +85C) Bus Clock Frequency (-40C to +85C) External Clock Input (XTALIN) External Clock Input (XTALIN) Voltage MINIMUM 1.71 V 2.0 V 3.0 V 3.14 V 1.71 V 10 MHz 10 MHz 10 MHz 10 MHz 14 MHz 1.71 V TYPICAL 1.8 V 2.1 V 3.3 V 3.3 V 1.8 V MAXIMUM 1.89 V 2.2 V 3.6 V 3.6 V 1.89 V 200 MHz 195 MHz 100 MHz 250 MHz 245 MHz 125 MHz NOTES 1, 4 1, 5 2, 6 2, 7 3, 4, 6 3, 4, 6 3, 4, 6 3, 5, 7 3, 5, 7 3, 5, 7 8 14.7456 MHz 1.8 V 20 MHz 1.89 V Operating Temperature -40C 25C +85C NOTES: 1. Core Voltage should never exceed I/O Voltage after initial power up. See "Power Supply Sequencing" on page 33 2. USB is not functional below 3.0 V 3. Using 14.7456 MHz Main Oscillator Crystal and 32.768 kHz RTC Oscillator Crystal 4. VDDC = 1.71 V to 1.89 V (LH7A400N0G000xx) 5. VDDC = 2.1 V 5 % (LH7A400N0G076xx only) 6. VDD = 3.0 V to 3.6 V (LH7A400N0G000xx) 7. VDD = 3.14V to 3.60 V (LH7A400N0G076xx only) 8. IMPORTANT: Most peripherals will NOT function with crystals other than 14.7456 MHz. Preliminary data sheet Rev. 01 -- 16 July 2007 29 LH7A400 NXP Semiconductors 32-Bit System-on-Chip 245 240 235 FREQUENCY (MHz) 230 225 220 215 210 205 200 195 25 35 45 55 TEMP (C) LH7A400-206 1.89 V (+5%) 1.80 V 65 75 1.71 V (-5%) 85 Figure 8. Temperature/Voltage/Speed Chart (For LH7A400N0G000xx) Table 9. Clock Frequency vs. Voltages (VDDC) vs. Temperature PARAMETER 25C 70C 85C Clock Frequency (FCLK) Clock Period (FCLK) Clock Frequency (FCLK) Clock Period (FCLK) Clock Frequency (FCLK) Clock Period (FCLK) 1.71 V 211 MHz 4.74 ns 200 MHz 5.00 ns 195 MHz 5.13 ns 1.8 V 225 MHz 4.44 ns 212 MHz 4.72 ns 208 MHz 4.81 ns 1.89 V 240 MHz 4.17 ns 227 MHz 4.41 ns 222 MHz 4.50 ns NOTES: 1. Table 9 is representative of a typical wafer process. Guaranteed values are in the Recommended Operating Conditions table. 2. LH7A400N0G000xx 30 Rev. 01 -- 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A400 DC/AC SPECIFICATIONS Unless otherwise noted, all data provided in these specifications are based on -40C to +85C, VDDC = 1.71 V to 1.89 V, VDD = 3.0 V to 3.6 V, VDDA = 1.71 V to 1.89 V. DC Specifications SYMBOL VIH VIL VHST VOH PARAMETER CMOS and Schmitt Trigger Input HIGH Voltage CMOS and Schmitt Trigger Input LOW Voltage Schmitt Trigger Hysteresis Output Drive 2 Output Drive 3 Output Drive 4 and 5 Output Drive 2 VOL Output Drive 3 Output Drive 4 Output Drive 5 Input Leakage Current IIN IOZ ISTARTUP IACTIVE IHALT CIN COUT Input Leakage Current (with pull-up resistors installed) Output Tri-state Leakage Current Startup Current Active Current Halt Current Input Capacitance Output Capacitance 125 25 42 4 4 MIN. 2.0 TYP. MAX. UNIT 5.5 0.8 V V V V V V 0.4 0.4 0.4 0.4 V V V V A A A A mA mA A pF pF VIL to VIH IOH = -4 mA IOH = -8 mA IOH = -12 mA IOL = 4 mA IOL = 8 mA IOL = 12 mA IOL = 20 mA VIN = VDD or GND VIN = VDD or GND VOUT = VDD or GND 2 1 1 CONDITIONS NOTES -0.2 0.25 2.6 2.6 2.6 -10 -200 -10 10 -20 10 50 180 41 ISTANDBY Standby Current NOTES: 1. Output Drive 5 can sink 20 mA of current, but sources 12 mA of current. 2. Current consumption until oscillators are stabilized. AC Test Conditions PARAMETER DC I/O Supply Voltage (VDD) DC Core Supply Voltage (VDDC) Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels RATING 3.0 to 3.6 1.71 to 1.89 VSS to 3 2 VDD/2 UNIT V V V ns V Preliminary data sheet Rev. 01 -- 16 July 2007 31 LH7A400 NXP Semiconductors 32-Bit System-on-Chip LH7A400N0G000xx (FCLK = 200 MHz) SYMBOL PARAMETER Maximum Specified Value The values specified in the MAXIMUM column were determined using these operating characteristics: * All IP blocks either operating or enabled at maximum frequency and size configuration * Core operating at maximum power configuration * All voltages at maximum specified values * Maximum specified ambient temperature (tAMB). Typical The values in the TYPICAL column were determined using a `typical' application under `typical' environmental conditions and the following operating characteristics: * LINUX operating system running from SDRAM * UART and AC97 peripherals operating; all other peripherals as needed by the OS * LCD enabled with 320 x 240 x 16-bit color, 60 Hz refresh rate, data in SDRAM * I/O loads at nominal * Cache enabled * FCLK = 200 MHz or 250 MHz; HCLK = 100 MHz or 125 MHz; PCLK = 50 MHz or 62.5 MHz * All voltages at typical values * Nominal case temperature (tAMB). ICORE IIO ICORE IIO ICORE IIO TYP. MAX. ACTIVE MODE Core Current I/ O Current Core Current I/ O Current Core Current I/ O Current 110 15 24 1 40 2 135 45 39 2 TYP. LH7A400N0G076xx (FCLK = 250 MHz) UNITS 250 mA mA 50 mA mA 125 4 A A CURRENT CONSUMPTION BY OPERATING MODE Current consumption can depend on a number of parameters. To make this data more usable, the values presented in Table 10 were derived under the conditions presented here. Table 10. Current Consumption by Mode HALT MODE (ALL PERIPHERALS DISABLED) STANDBY MODE (TYPICAL CONDITIONS ONLY) PERIPHERAL CURRENT CONSUMPTION In addition to the modal current consumption, Table 11 shows the typical current consumption for each of the on-board peripheral blocks. The values were determined with the CPU clock running at 200 MHz, typical conditions, and no I/O loads. This current is supplied by the 1.8 VDDC power supply. Table 11. Peripheral Current Consumption PERIPHERAL AC97 UART (Each) RTC Timers (Each) LCD (+I/O) MMC SCI PWM (each) BMI-SWI BMI-SBus SDRAM (+I/O) USB (+PLL) ACI TYPICAL 1.3 1.0 0.005 0.1 5.4 (1.0) 0.6 23 < 0.1 1.0 1.0 1.5 (14.8) 5.6 (3.3) 0.8 UNITS mA mA mA mA mA mA mA mA mA mA mA mA mA 32 Rev. 01 -- 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A400 Power Supply Sequencing NXP recommends that the 1.8 V power supply be energized before the 3.3 V supply. If this is not possible, the 1.8 V supply may not lag the 3.3 V supply by more than 100 s. If longer delay time is needed, it is recommended that the voltage difference between the two power supplies be within 1.5 V during power supply ramp up. To avoid a potential latchup condition, voltage should be applied to input pins only after the device is powered-on as described above. * ACBITCLK, AC97 clock * SCLK, Synchronous Memory clock. All signal transitions are measured at the 50 % point. For outputs from the LH7A400, tOVXXX (e.g. tOVA) represents the amount of time for the output to become valid from a valid address bus, or rising edge of the peripheral clock. Maximum requirements for tOVXXX are shown in Table 12. The signal tOHXXX (e.g. tOHA) represents the amount of time the output will be held valid from the valid address bus, or rising edge of the peripheral clock. Minimum requirements for tOHXXX are listed in Table 12. For Inputs, tISXXX (e.g. tISD) represents the amount of time the input signal must be valid before a valid address bus, or rising edge of the peripheral clock (except SSP and ACI). Maximum requirements for tISXXX are shown in Table 12. The signal tIHXXX (e.g. tIHD) represents the amount of time the output must be held valid from the valid address bus, or rising edge of the peripheral clock (except SSP and ACI). Minimum requirements are shown in Table 12. AC Specifications All signals described in Table 12 relate to transitions after a reference clock signal. The illustration in Figure 9 represents all cases of these sets of measurement parameters. The reference clock signals in this design are: * HCLK, internal System Bus clock (`C' in timing data) * PCLK, Peripheral Bus clock * SSPCLK, Synchronous Serial Port clock * UARTCLK, UART Interface clock * LCDDCLK, LCD Data clock from the LCD Controller REFERENCE CLOCK tOVXXX tOHXXX OUTPUT SIGNAL (O) tISXXX tIHXXX INPUT SIGNAL (I) 7A400-28 Figure 9. LH7A400 Signal Timing Preliminary data sheet Rev. 01 -- 16 July 2007 33 LH7A400 NXP Semiconductors 32-Bit System-on-Chip Table 12. AC Signal Characteristics SIGNAL TYPE Output A[27:0] Output -- LOAD 50 pF 50 pF -- SYMBOL tRC tWC tWS tDVWE Output 50 pF tDHWE tDVBE tDHBE D[31:0] Input -- tDSCS tDHCS tDSOE tDHOE tDSBE tDHBE tCS nCS[7:0] Output 30 pF tAVCS tAHCS tOVA tOHA tOVB tOHD tOVD tISD tIHD 30 pF 30 pF 30 pF 30 pF 30 pF 30 pF tOVCA tOHCA tOVRA tOHRA tOVSDW tOHSDW tOVC tOVDQ tOVSC tOHSC tOVDREG tOHDREG tOVD tOHD tISD tIHD 30 pF 30 pF 30 pF 30 pF 30 pF tOVCE1 tOHCE1 tOVCE2 tOHCE2 tOVOE tOHOE tOVWE tOHWE tOVPCD tOHPCD 4 x tHCLK - 5 ns 3 x tHCLK - 5 ns tHCLK 3 x tHCLK - 5 ns tHCLK + 1 ns 4 x tHCLK - 5 ns tHCLK + 1 ns 4 x tHCLK - 5 ns tHCLK 4 x tHCLK - 5 ns tHCLK 4 x tHCLK - 5 ns tHCLK - 10 ns 4 x tHCLK - 5 ns tHCLK 1.5ns 2 ns 1.5 /2.5 ns 1.03/1.54 ns 2 ns 1.53/24 ns 2 ns 1.5 3/24 3 4 MIN. 4 x tHCLK - 7.0 ns 4 x tHCLK - 7.0 ns tHCLK ns tHCLK - 6.0 ns tHCLK - 7.0 ns tHCLK - 5.0 ns tHCLK - 7.0 ns 15 ns 0 ns 15 ns 0 ns 15 ns 0 ns 2 x tHCLK - 3.0 ns tHCLK - 4.0 ns tHCLK MAX. 4 x tHCLK + 7.5 ns 4 x tHCLK + 7.5 ns tHCLK ns tHCLK - 2.0 ns tHCLK + 2.0 ns tHCLK - 1.0 ns tHCLK + 3.0 ns -- -- -- -- -- -- 2 x tHCLK + 3.0 ns tHCLK tHCLK + 4.5 ns 5.53/7.54 ns DESCRIPTION Read Cycle Time Write Cycle Time Wait State Width Data Valid to Write Edge (nWE invalid) Data Hold after Write Edge (nWE invalid) Data Valid to nBLE Invalid Data Hold after nBLE Invalid Data Setup to nCSx Invalid Data Hold to nCSx Invalid Data Setup to nOE Invalid Data Hold to nOE Invalid Data Setup to nBLE Invalid Data Hold to nBLE Invalid nCSx Width Address Valid to nCSx Valid Address Hold after nCSx Invalid Address Valid Address Hold Bank Select Valid Data Hold Data Valid Data Setup Data Hold ASYNCHRONOUS MEMORY INTERFACE SIGNALS (+ [wait states x HCLK period])1 SYNCHRONOUS MEMORY INTERFACE SIGNALS SA[13:0] SA[17:16]/SB[1:0] Output Output Output D[31:0] Input nCAS nRAS nSWE SCKE[1:0] DQM[3:0] nSCS[3:0] Output Output Output Output Output Output 50 pF 50 pF 50 pF 1.5 /1.5 ns 5.53/7.54 ns 5.53/7.54 ns 3 4 5.53/7.54 ns 5.53/7.54 ns ns 5.53/7.54 ns 5.53/7.54 ns 5.53/7.54 ns 5.53/7.54 ns CAS Valid CAS Hold RAS Valid RAS Hold Write Enable Valid Write Enable Hold Clock Enable Valid Data Mask Valid Synchronous Chip Select Valid Synchronous Chip Select Hold 2 ns 1.53/24 ns 2 ns 2 ns 2 ns 1.53/24 ns PCMCIA INTERFACE SIGNALS (+ wait states x HCLK period) nPCREG Output Output D[31:0] Input nPCCE1 nPCCE2 nPCOE nPCWE PCDIR Output Output Output Output Output 30 pF 50 pF tHCLK nREG Valid nREG Hold Data Valid Data Hold Data Setup Time Data Hold Time Chip Enable 1 Valid Chip Enable 1 Hold Chip Enable 2 Valid Chip Enable 2 Hold Output Enable Valid Output Enable Hold Write Enable Valid Write Enable Hold Card Direction Valid Card Direction Hold 34 Rev. 01 -- 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A400 Table 12. AC Signal Characteristics (Cont'd) SIGNAL TYPE LOAD SYMBOL tOS tOH tOS tOH tIS tIH tIS tIH tOVAC97 tOHAC97 tISAC97 tIHAC97 tACBITCLK tOVSSPFRM tOHSSPFRM 50 pF tOVSSPOUT tOHSSPOUT tISSSPIN tSSPCLK tOVD tOHD tIS tIH 30 pF tOV 10 ns 10 ns 2.5 ns COLOR LCD CONTROLLER LCDVD [17:0] Output -- 3 ns LCD Data Clock to Data Valid 5 ns 14 ns 8.819 ms 271 ns 15 ns AUDIO CODEC INTERFACE (ACI) ACOUT ACIN Output Input 30 pF ACOUT delay from rising clock edge ACOUT Hold ACIN Setup ACIN Hold 5 ns 10 ns 10 ns 10 ns 2.5 ns 72 ns 90 ns 10 ns MIN. 5 ns 5 ns 5 ns 5 ns 3 ns 3 ns 3 ns 3 ns AC97 INTERFACE SIGNALS ACOUT/ACSYNC ACIN ACBITCLK Output Input Input 30 pF 15 ns AC97 Output Valid/Sync Valid AC97 Output Hold/Sync Hold AC97 Input Setup AC97 Input Hold AC97 Clock Period SSPFRM Valid SSPFRM Hold SSP Transmit Valid SSP Transmit Hold SSP Receive Setup SSP Clock Period MAX. DESCRIPTION MMC Command Setup MMC Command Hold MMC Data Setup MMC Data Hold MMC Data Setup MMC Data Hold MMC Command Setup MMC Command Hold MMC INTERFACE SIGNALS MMCCMD MMCDATA MMCDATA MMCCMD Output Output Input Input 100 pF 100 pF SYNCHRONOUS SERIAL PORT (SSP) SSPFRM SSPTX SSPRX SSPCLK Output Output Input Output NOTES: 1. Register BCRx:WST1 = 0b000 2. For Output Drive strength specifications, refer to Table 3 3. LH7A400N0G076xx only 4. LH7A400N0G000xx only Preliminary data sheet Rev. 01 -- 16 July 2007 35 LH7A400 NXP Semiconductors 32-Bit System-on-Chip SMC Waveforms Figure 10 and Figure 11 show the waveform and timing for an External Asynchronous Memory Write. Note that the deassertion of nWE can precede the deassertion of nCS by a maximum of one HCLK, or at minimum, can coincide (see Table 12). Figure 12 and Figure 13 show the waveform and timing for an External Asynchronous Memory Read. 0 HCLK 1 2 3 4 tWC A[27:0] VALID ADDRESS tDVWE, tDVBE tDHWE, tDHBE D[31:0] VALID DATA tAVCS tCS tAHCS nCSx tAVWE nCS Valid tWE tCSHWE nWE nWE Valid WRITE EDGE tAVBE tBEW tCSHBE nBLE nBLE Valid LH7A400-201 Figure 10. External Asynchronous Memory Write with 0 Wait States (BCRx:WST1 = 0b000) 36 Rev. 01 -- 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A400 0 HCLK 1 2 3 4 5 6 7 8 A[27:0] VALID ADDRESS D[31:0] VALID DATA nCSx nCSx Valid WRITE EDGE nWE nWE Valid nBLE nBLE Valid WAIT WAIT WAIT WAIT STATE 1 STATE 2 STATE 3 STATE 4 0 WAIT STATE tWS tWS tWS tWS LH7A400-203 Figure 11. External Asynchronous Memory Write with 4 Wait States (BCRx:WST1 = 0b100) Preliminary data sheet Rev. 01 -- 16 July 2007 37 LH7A400 NXP Semiconductors 32-Bit System-on-Chip 0 HCLK 1 2 3 4 tRC tAHCS, tAHOE, tAHBE A[27:0] VALID ADDRESS D[31:0] VALID DATA tDSCS tAVCS tCS DATA LATCHED HERE tDHCS nCSx nCS Valid tDSOE tAVOE tOE tDHOE nOE nOE Valid tDSBE tAVBE tBER tDHBE nBLE nBLE Valid LH7A400-200 Figure 12. External Asynchronous Memory Read with 0 Wait States (BCRx:WST1 = 0b000) 38 Rev. 01 -- 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A400 0 HCLK 1 2 3 4 5 6 7 8 9 10 A[27:0] VALID ADDRESS nCS[3:0, CS[7:6] nCSx Valid nOE nOE Valid nBLE nBLE Valid D[31:0] VALID DATA 0 WAIT STATE, DATA WOULD BE LATCHED HERE WAIT WAIT WAIT WAIT STATE 1 STATE 2 STATE 3 STATE 4 tWS tWS tWS tWS 4 WAIT STATES, DATA LATCHED HERE LH7A400-202 Figure 13. External Asynchronous Memory Read with 4 Wait States (BCRx:WST1 = 0b100) Synchronous Memory Controller Waveforms Figure 14 shows the timing for a Synchronous Burst Read (page already open). Figure 15 shows the timing for Activate a Bank and Write. Figure 16 and Figure 17 show Texas Instruments synchronous serial frame format, Figure 18 through Figure 25 show the Motorola SPI format, and Figure 26 and Figure 27 show National Semiconductor's MICROWIRE data frame format. For Texas Instruments SSI format, the SSPFRM pin is pulsed prior to each frame's transmission for one serial clock period beginning at its rising edge. For this frame format, both the SSP and the external slave device drive their output data on the rising edge of the clock and latch data from the other device on the falling edge. See Figure 16 and Figure 17. SSP Waveforms The Synchronous Serial Port (SSP) supports three data frame formats: * Texas Instruments SSI * Motorola SPI * National Semiconductor MICROWIRE Each frame format is between 4 and 16 bits in length, depending upon the programmed data size. Each data frame is transmitted beginning with the Most Significant Bit (MSB) i.e. `big endian'. For all three formats, the SSP serial clock is held LOW (inactive) while the SSP is idle. The SSP serial clock transitions only during active transmission of data. The SSPFRM signal marks the beginning and end of a frame. The SSPEN signal controls an off-chip line driver's output enable pin. Preliminary data sheet Rev. 01 -- 16 July 2007 39 LH7A400 NXP Semiconductors 32-Bit System-on-Chip tSCLK SCLK tOHXXX SDRAMcmd READ tOHA, tOHB tOVXXX nDQM SA[13:0], SB[1:0] tOVA, tOVB D[31:0] NOTES: 1. SDRAMcmd is the combination of nRAS, nCAS, nSWE, and nSCSx. 2. tOVXXX represents tOVRA, tOVCA, tOVSVW, or tOVSC. 3. tOHXXX represents tOHRA, tOHCA, tOHSVW, or tOHSC. 4. DQM[3:0] is static LOW. 5. SCKE is static HIGH. BANK, COLUMN tISD tIHD DATA n DATA n + 2 DATA n + 1 DATA n + 3 LH7A400-23 Figure 14. Synchronous Burst Read SCLK tOVC SCKE tOVXXX tOHXXX SDRAMcmd ACTIVE tOHA WRITE SA[13:0], SB[1:0] BANK, ROW tOVA D[31:0] tOVD tOHD NOTES: 1. SDRAMcmd is the combination of nRAS, nCAS, nSWE, and nSCSx. 2. tOVXXX represents tOVRA, tOVCA, tOVSVW, or tOVSC. Refer to the AC timing table. 3. tOHXXX represents tOHRA, tOHCA, tOHSVW, or tOHSC. LH7A400-24 BANK, COLUMN DATA Figure 15. Synchronous Bank Activate and Write 40 Rev. 01 -- 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A400 SSPCLK SSPFRM SSPTXD/ SSPRXD MSB 4 to 16 BITS LSB LH7A400-97 Figure 16. Texas Instruments Synchronous Serial Frame Format (Single Transfer) SSPCLK SSPFRM SSPTXD/ SSPRXD MSB 4 to 16 BITS LH7A400-98 LSB Figure 17. Texas Instruments Synchronous Serial Frame Format (Continuous Transfer) SSPCLK nSSPFRM SSPRXD MSB LSB Q 4 to 16 BITS SSPTXD NOTE: Q is undefined. MSB LSB LH7A400-99 Figure 18. Motorola SPI Frame Format (Single Transfer) with SPO = 0 and SPH = 0 Preliminary data sheet Rev. 01 -- 16 July 2007 41 LH7A400 NXP Semiconductors 32-Bit System-on-Chip SSPCLK nSSPFRM SSPTXD/ SSSRXD LSB MSB 4 to 16 BITS LSB MSB LH7A400-100 Figure 19. Motorola SPI Frame Format (Continuous Transfer) with SPO = 0 and SPH = 0 SSPCLK nSSPFRM SSPRXD Q MSB LSB Q 4 to 16 BITS SSPTXD NOTE: Q is undefined. MSB LSB LH7A400-101 Figure 20. Motorola SPI Frame Format (Single Transfer) with SPO = 0 and SPH = 1 SSPCLK nSSPFRM SSPTXD/ SSSRXD LSB MSB 4 to 16 BITS LSB MSB LH7A400-102 Figure 21. Motorola SPI Frame Format (Continuous Transfer) with SPO = 0 and SPH = 1 SSPCLK nSSPFRM SSPTXD/ SSSRXD LSB MSB 4 to 16 BITS LSB MSB LH7A400-103 Figure 22. Motorola SPI Frame Format (Continuous Transfer) with SPO = 1 and SPH = 1 42 Rev. 01 -- 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A400 SSPCLK nSSPFRM SSPRXD MSB LSB Q 4 to 16 BITS SSPTXD MSB LSB NOTE: Q is undefined. LH7A400-104 Figure 23. Motorola SPI Frame Format (Single Transfer) with SPO = 1 and SPH = 0 SSPCLK nSSPFRM SSPTXD/ SSPRXD LSB MSB LSB MSB 4 to 16 BITS LH7A400-105 Figure 24. Motorola SPI Frame Format (Continuous Transfer) with SPO = 1 and SPH = 0 SSPCLK nSSPFRM SSPRXD Q MSB LSB Q 4 to 16 BITS SSPTXD NOTE: Q is undefined. MSB LSB LH7A400-106 Figure 25. Motorola SPI Frame Format (Single Transfer) with SPO = 1 and SPH = 1 Preliminary data sheet Rev. 01 -- 16 July 2007 43 LH7A400 NXP Semiconductors 32-Bit System-on-Chip For National Semiconductor MICROWIRE format, the serial frame pin (SSPFRM) is active LOW. Both the SSP and external slave device drive their output data on the falling edge of the clock, and latch data from the other device on the rising edge of the clock. Unlike the full-duplex transmission of the other two frame formats, the National Semiconductor MICROWIRE format utilizes a master-slave messaging technique that operates in half-duplex. When a frame begins in this mode, an 8-bit control message is transmitted to the off-chip slave. During this transmission no incoming data is received by the SSP. After the message has been sent, the external slave device decodes the message. After waiting one serial clock period after the last bit of the 8bit control message was received it responds by returning the requested data. The returned data can be 4 to 16 bits in length, making the total frame length between 13 to 25 bits. See Figure 26 and Figure 27. SSPCLK nSSPFRM SSPTXD MSB LSB 8-BIT CONTROL SSPRXD 0 MSB LSB 4 to 16 BITS OUTPUT DATA LH7A400-107 Figure 26. MICROWIRE Frame Format (Single Transfer) SSPCLK nSSPFRM SSPTXD LSB MSB LSB 8-BIT CONTROL SSPRXD 0 MSB LSB MSB 4 to 16 BITS OUTPUT DATA LH7A400-108 Figure 27. MICROWIRE Frame Format (Continuous Transfers) 44 Rev. 01 -- 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A400 PC Card (PCMCIA) Waveforms Figure 28 shows the waveforms and timing for a PCMCIA Read Transfer, Figure 29 shows the waveforms and timing for a PCMCIA Write Transfer. PRECHARGE ACCESS HOLD TIME TIME TIME (See Note 1) (See Note 1) (See Note 1) HCLK A[25:0] ADDRESS nPCREG tOVDREG tOHDREG nPCCEx (See Note 2) tOVCEx tOHCEx PCDIR tOVPCD tOHPCD D[15:0] tISD tIHD nPCOE tOVOE tOHOE NOTES: 1. Precharge time, access time, and hold time are programmable wait-state times. 2. nPCCE1 nPCCE2 0 0 0 1 1 0 1 1 TRANSFER TYPE Common Memory Attribute Memory I/O None DATA LH7A400-11 Figure 28. PCMCIA Read Transfer Preliminary data sheet Rev. 01 -- 16 July 2007 45 LH7A400 NXP Semiconductors 32-Bit System-on-Chip PRECHARGE ACCESS HOLD TIME TIME TIME (See Note 1) (See Note 1) (See Note 1) HCLK A[25:0] ADDRESS nPCREG tOVDREG tOHDREG nPCCEx (See Note 2) tOVCEx tOHCEx PCDIR tOVPCD DATA tOVD tOHD D[15:0] nPCWE tOVWE tOHWE NOTES: 1. Precharge time, access time, and hold time are programmable wait-state times. 2. nPCCE1 nPCCE2 0 0 0 1 1 0 1 1 TRANSFER TYPE Common Memory Attribute Memory I/O None LH7A400-12 Figure 29. PCMCIA Write Transfer ACCESS nPCWE, nPCOE PRECHARGE HOLD nCSx LH7A400-209 Figure 30. PCMCIA Precharge, Access, and Hold Waveform 46 Rev. 01 -- 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A400 MMC Interface Waveform Figure 31 shows the waveforms and timing for an MMC command or data Read and Write. AC97 Interface Waveform Figure 32 shows the waveforms and timing for the AC97 interface Data Setup and Hold. MMC CLOCK tIS tIH SOC INPUT DATA/CMD DATA tOS tOH SOC OUTPUT DATA /CMD INVALID DATA INVALID LH7A400-14 Figure 31. MMC Command/Data Read and Write Timing tACBITCLK ACBITCLK tOVAC97 ACOUT/ACSYNC tISAC97 tIHAC97 ACIN LH7A400-16 tOHAC97 Figure 32. AC97 Data Setup and Hold Preliminary data sheet Rev. 01 -- 16 July 2007 47 LH7A400 NXP Semiconductors 32-Bit System-on-Chip Audio Codec Interface Waveforms Figure 33 and Figure 34 show the timing for the ACI. Transmit data is clocked on the rising edge of ACBITCLK (whether transmitted by the LH7A400 ACI or by the external codec chip); receive data is clocked on the falling edge. This allows full-speed, full duplex operation. Color LCD Controller Waveforms Figure 35 shows the Valid Output Setup Time for LCD data. Timing diagrams for each CLCDC mode appear in Figure 36 through Figure 41. ACBITCLK ACSYNC/ACOUT tOS tOH ACIN tIS tIH LH7A400-169 Figure 33. ACI Signal Timing ACBITCLK ACSYNC BIT ACIN/ACOUT 7 6 5 4 3 2 1 0 7 6 ACIN/ACOUT SAMPLED ON FALLING EDGE LH7A400-181 Figure 34. ACI Data stream LCDDCLK tOV LCDVD (SoC Output) DATA VALID LH7A400-211 Figure 35. CLCDC Valid Output Data Time 48 Rev. 01 -- 16 July 2007 Preliminary data sheet Preliminary data sheet 1 STN HORIZONTAL LINE TIMING0:HSW LCDDCLK IS SUPPRESSED DURING LCDLLP TIMING0:HBP TIMING0:PPL TIMING0:HFP HORIZONTAL BACK PORCH ENUMERATED IN 'LCDDCLKS' D001 D002 D.... DNNN HORIZONTAL FRONT PORCH ONE 'LINE' OF LCD DATA ENUMERATED IN 'LCDDCLKS' LH7A400-113 32-Bit System-on-Chip CLCDC CLOCK (INTERNAL) R8 LCDLP (LINE SYNC PULSE) TIMING2:IHS Figure 36. STN Horizontal Timing Diagram Rev. 01 -- 16 July 2007 NXP Semiconductors N9 LCDDCLK (PANEL DATA CLOCK) TIMING2:PCD TIMING2:BCD TIMING2:IPC TIMING2:CPL LCDVD[17:0] (LCD DATA) THE ACTIVE DATA LINES WILL VARY WITH THE TYPE OF STN PANEL: 4-BIT, 8-BIT, COLOR, OR MONO NOTE: Circled numbers are LH7A400 pin numbers. LH7A400 49 50 DISPLAY-DEPENDENT TURN-ON DELAY 1 STN FRAME DISPLAY-DEPENDENT TURN-OFF DELAY PANEL POSITIVE HIGH-VOLTAGE SUPPLY ACTIVE PANEL NEGATIVE HIGH-VOLTAGE SUPPLY ACTIVE PANEL LOGIC ACTIVE PANEL DATA CLOCK ACTIVE AC BIAS ACTIVE TIMING1:VSW = 0 TIMING1: VBP TIMING1:LPP TIMING1:VFP BACK PORCH ENUMERATED IN HORIZONTAL 'LINES' ALL 'LINES' FOR ONE FRAME FRONT PORCH ENUMERATED IN HORIZONTAL 'LINES' SEE 'STN HORIZONTAL TIMING DIAGRAM' LH7A400-112 LH7A400 VDD VSS R1 LCDVDDEN (DISPLAY ENABLE) N9 LCDDCLK (PANEL DATA CLOCK) TIMING2:PCD TIMING2:BCD TIMING2:IPC TIMING2:CPL LCDMux:PIN133 Figure 37. STN Vertical Timing Diagram Rev. 01 -- 16 July 2007 NXP Semiconductors P9 LCDENAB (AC BIAS) TIMING2:ACB R6 LCDFP (FRAME PULSE) TIMING1:IVS (See Note 2) PIXEL DATA AND HORIZONTAL CONTROL SIGNALS FOR ONE FRAME NOTES: 1. Signal polarties may vary for some displays. 2. LCDFP with TIMING1:VSW = 0 is only a single horizontal ine period. 32-Bit System-on-Chip Preliminary data sheet 3. Circled numbers are LH7A400 pin numbers. Preliminary data sheet 1 TFT HORIZONTAL LINE TIMING0:HSW TIMING0:HBP 32-Bit System-on-Chip CLCDC CLOCK (INTERNAL) R8 LCDLLP (HORIZ. SYNC PULSE) TIMING2:IHS Figure 38. TFT Horizontal Timing Diagram Rev. 01 -- 16 July 2007 HORIZONTAL BACK PORCH ENUMERATED IN 'LCDDCLKS' D001 D002 D.... NXP Semiconductors N9 LCDDCLK (PANEL DATA CLOCK) TIMING2:PCD TIMING2:BCD TIMING2:IPC TIMING2:CPL 16 x (TIMING0:PPL+1) TIMING0:HFP DNNN LCDVD[17:0] (LCD DATA) HORIZONTAL FRONT PORCH ONE 'LINE' OF LCD DATA ENUMERATED IN 'LCDDCLKS' NOTE: Circled numbers are LH7A400 pin numbers. LH7A400-192 LH7A400 51 52 DISPLAY-DEPENDENT TURN-ON DELAY 1 TFT FRAME DISPLAY DEPENDENT TURN-OFF DELAY PANEL POSITIVE HIGH-VOLTAGE SUPPLY ACTIVE PANEL NEGATIVE HIGH-VOLTAGE SUPPLY ACTIVE PANEL LOGIC ACTIVE PANEL DATA CLOCK ACTIVE DATA ENABLE TIMING1: VSW TIMING1:VBP TIMING1:LPP TIMING1: VFP BACK PORCH ENUMERATED IN HORIZONTAL 'LINES' ALL 'LINES' FOR ONE FRAME FRONT PORCH ENUMERATED IN HORIZONTAL 'LINES' SEE 'TFT HORIZONTAL TIMING DIAGRAM' LH7A400-109 LH7A400 VDD VSS See Note 2 R1 LCDVDDEN (ENABLE FOR LOW-VOLTAGE DIGITAL LOGIC AND ANALOG SUPPLIES) N9 LCDDCLK (PANEL DATA CLOCK) TIMING2:PCD TIMING2:BCD TIMING2:IPC Figure 39. TFT Vertical Timing Diagram Rev. 01 -- 16 July 2007 NXP Semiconductors P9 LCDENAB (DATA ENABLE) TIMING2:IOE R6 LCDFP (VERTICAL SYNC PULSE) TIMING1:IVS PIXEL DATA AND HORIZONTAL CONTROL SIGNALS FOR ONE FRAME NOTES: 1. Signal polarties may vary for some displays. 2. The use of LCDVDDEN for high-voltage power control is optional on some TFT panels. 32-Bit System-on-Chip Preliminary data sheet 3. Circled numbers are LH7A400 pin numbers. 32-Bit System-on-Chip NXP Semiconductors LH7A400 1 AD-TFT or HR-TFT HORIZONTAL LINE CLCDC CLOCK (INTERNAL) TIMING0:HSW R8 LCDLP (HORIZONTAL SYNC PULSE) INPUTS TO THE ALI FROM THE CLCDC LCDDCLK (PANEL DATA CLOCK) TIMING2:PCD TIMING2:BCD TIMING2:IPC TIMING2:CPL LCDVD[17:0] 16 x (TIMING0:PPL+1) TIMING0:HSW + TIMING0:HBP LCDENAB (INTERNAL DATA ENABLE) 001 002 003 004 005 006 007 008 PIXEL DATA 320 N9 LCDDCLK (DELAYED FOR HR-TFT) LCDVD[17:0] (DELAYED FOR HR-TFT) 001 002 003 004 005 006 317 318 319 320 1 LCDDCLK ALITIMING2:SPLDEL OUTPUTS FROM THE ALI TO THE PANEL R2 LCDSPL (LINE START PULSE LEFT) 1 LCDDCLK R8 LCDLP (HORIZONTAL SYNC PULSE) ALITIMING1:LPDEL ALITIMING1:PSCLS ALITIMING2:PS2CLS2 T1 LCDCLS P2 LCDPS ALITIMING1:REVDEL K6 LCDREV NOTE: Circled numbers are LHA400 pin numbers. LH7A400-111 Figure 40. AD-TFT and HR-TFT Horizontal Timing Diagram Preliminary data sheet Rev. 01 -- 16 July 2007 53 LH7A400 NXP Semiconductors 32-Bit System-on-Chip TIMING1:VSW LCDSPS (Vertical Sync) 1.5 s - 4 s LCDHRLP (Horizontal Sync) LCDVD (LCD Data) 2x H-LINE R2 LCDSPL L8 T2 LH7A400-66 Figure 41. AD-TFT and HR-TFT Vertical Timing Diagram CLOCK AND STATE CONTROLLER (CSC) WAVEFORMS Figure 42 shows the behavior of the LH7A400 when coming out of Reset or Power On. Figure 43 shows external reset timing, and Table 13 gives the timing parameters. Figure 44 depicts signal timing following a Reset. At Power-On, nPOR must be held LOW at least until the 32.768 kHz oscillator is stable, and must be deasserted at least two 32.768 kHz clock periods before the WAKEUP signal is asserted. Once the 14.7456 MHz oscillator is stable, the PLLs require 250 s to lock. On transition from Standby to Run (including a Cold Boot), the Wakeup pin must not be asserted for 2 seconds after assertion of nPOR to allow time for sampling BATOK and nEXTPWR. The delay prevents a false `battery good' indication caused by alkaline battery recovery that can immediately follow a battery-low switch off. The battery sampling takes place on the rising edge of the 1 Hz clock. This clock is derived from the 32.768 kHz oscillator. The WAKEUP pin can be pulsed, but at least one edge must follow the 2 second delay to be recognized. For more information, see the application note "Implementing Auto-Wakeup on the LH7A4xx Series Devices" at www.nxp.com. Figure 45 shows the recommended components for the NXP LH7A400 32.768 kHz external oscillator circuit. Figure 46 shows the same for the 14.7456 MHz external oscillator circuit. In both figures, the NAND gate represents the internal logic of the chip. Table 13. Reset AC Timing PARAMETER tOSC32 tOSC14 DESCRIPTION 32.768 kHz Oscillator Stabilization Time after Power On* 14.7456 MHz Oscillator Stabilization Time after Wake UP 4 MIN. MAX. 550 4 UNIT ms ms 32.768 kHz clock periods tURESET/tPWRFL nURESET/nPWRFL Pulse Width NOTE: *VDDC = VDDCmin 54 Rev. 01 -- 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A400 VDDCmin VDDC XTAL32 tOSC32 WAKEUP tOSC14 XTAL14 nPOR LH7A400-25 Figure 42. Oscillator Start-up tURESET tPWRFL nURESET nPWRFL LH7A400-26 Figure 43. External Reset nPOR 2 sec. WAKEUP (asynchronous) 7.8125 ms CLKEN 7.8125 ms HCLK START UP STABLE CLOCK LH7A400-175 Figure 44. Signal Timing After Reset Preliminary data sheet Rev. 01 -- 16 July 2007 55 LH7A400 NXP Semiconductors 32-Bit System-on-Chip ENABLE INTERNAL TO THE LH7A400 EXTERNAL TO THE LH7A400 XTALIN XTALOUT Y1 32.768 kHz R1 18 M C1 15 pF GND NOTES: 1. Y1 is a parallel-resonant type crystal. (See table) 2. The nominal values for C1 and C2 shown are for a crystal specified at 12.5 pF load capacitance (CL). 3. The values for C1 and C2 are dependent upon the cystal's specified load capacitance and PCB stray capacitance. 4. R1 must be in the circuit. 5. Ground connections should be short and return to the ground plane which is connected to the processor's core ground pins. 6. Tolerance for R1, C1, C2 is 5%. C2 18 pF GND RECOMMENDED CRYSTAL SPECIFICATIONS PARAMETER 32.768 kHz Crystal Tolerance Aging Load Capacitance ESR (MAX.) Drive Level Recommended Part DESCRIPTION Parallel Mode 30 ppm 3 ppm 12.5 pF 50 k 1.0 W (MAX.) MTRON SX1555 or equivalent LH7A400-187 Figure 45. 32.768 kHz External Oscillator Components and Schematic 56 Rev. 01 -- 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A400 ENABLE INTERNAL TO THE LH7A400 EXTERNAL TO THE LH7A400 XTALIN XTALOUT Y1 14.7456 MHz R1 1 M C1 18 pF GND C2 22 pF GND RECOMMENDED CRYSTAL SPECIFICATIONS NOTES: 1. Y1 is a parallel-resonant type crystal. (See table) 2. The nominal values for C1 and C2 shown are for a crystal specified at 18 pF load capacitance (CL). 3. The values for C1 and C2 are dependent upon the cystal's specified load capacitance and PCB stray capacitance. 4. R1 must be in the circuit. 5. Ground connections should be short and return to the ground plane which is connected to the processor's core ground pins. 6. Tolerance for R1, C1, C2 is 5%. PARAMETER 14.7456 MHz Crystal Tolerance Stability Aging Load Capacitance ESR (MAX.) Drive Level Recommended Part DESCRIPTION (AT-Cut) Parallel Mode 50 ppm 100 ppm 5 ppm 18 pF 40 100 W (MAX.) MTRON SX2050 or equivalent LH7A400-188 Figure 46. 14.7456 MHz External Oscillator Components and Schematic Preliminary data sheet Rev. 01 -- 16 July 2007 57 LH7A400 NXP Semiconductors 32-Bit System-on-Chip Operating Temperature and Noise Immunity The junction temperature, Tj, is the operating temperature of the transistors in the integrated circuit. The switching speed of the CMOS circuitry within the SoC depends partly on Tj, and the lower the operating temperature, the faster the CMOS circuits will switch. Increased switching noise generated by faster switching circuits could affect the overall system stability. The amount of switching noise is directly affected by the application executed on the SoC. NXP recommends that users implementing a system to meet industrial temperature standards should use an external oscillator rather than a crystal to drive the system clock input of the System-on-Chip. This change from crystal to oscillator will increase the robustness (i.e., noise immunity of the clock input to the SoC). VDDC (SOURCE) VDDC LH7A400 10 H VDDA + 22 F 0.1 F VSSA LH7A400-189 Figure 47. VDDA, VSSA Filter Circuit UNUSED INPUT SIGNAL CONDITIONING Floating input signals can cause excessive power consumption. Unused inputs without internal pull-up or pull-down resistors should be pulled up or down externally (NXP recommends tying HIGH), to tie the signal to its inactive state. 33 K or less is recommended. Some GPIO signals default to inputs. If the pins that carry these signals are unused, software can program these signals as outputs, eliminating the need for pullups or pull-downs. Power consumption may be higher than expected until software completes programming the GPIO. Some LH7A400 inputs have internal pullups or pull-downs. If unused, these inputs do not require external conditioning. OTHER CIRCUIT BOARD LAYOUT PRACTICES All outputs have fast rise and fall times. Printed circuit trace interconnection length must therefore be reduced to minimize overshoot, undershoot and reflections caused by transmission line effects of these fast output switching times. This recommendation particularly applies to the address and data buses. When considering capacitance, calculations must consider all device loads and capacitances due to the circuit board traces. Capacitance due to the traces will depend upon a number of factors, including the trace width, dielectric material the circuit board is made from and proximity to ground and power planes. Attention to power supply decoupling and printed circuit board layout becomes more critical in systems with higher capacitive loads. As these capacitive loads increase, transient currents in the power supply and ground return paths also increase. Printed Circuit Board Layout Practices LH7A400 POWER SUPPLY DECOUPLING The LH7A400 has separate power and ground pins for different internal circuitry sections. The VDD and VSS pins supply power to I/O buffers, while VDDC and VSSC supply power to the core logic, and VDDA/VSSA supply analog power to the PLLs. Each of the VDD and VDDC pins must be provided with a low impedance path to the corresponding board power supply. Likewise, the VSS, VSSA, and VSSC pins must be provided with a low impedance path to the board ground. Each power supply must be decoupled to ground using at least one 0.1 F high frequency capacitor located as close as possible to a VDDx, VSSx pin pair on each of the four sides of the chip. If room on the circuit board allows, add one 0.01 F high frequency capacitor near each VDDx, VSSx pair on the chip. To be effective, the capacitor leads and associated circuit board traces connecting to the chip VDDx, VSSx pins must be kept to less than half an inch (12.7 mm) per capacitor lead. There must be one bulk 10 F capacitor for each power supply placed near one side of the chip. RECOMMENDED PLL, VDDA, VSSA FILTER The VDDA pins supply power to the chip PLL circuitry. VSSA is the ground return path for the PLL circuit. NXP recommends a low-pass filter attached as shown in Figure 47. The values of the inductor and capacitors are not critical. The low-pass filter prevents high frequency noise from adversely affecting the PLL circuits. The distance from the IC pin to the high frequency capacitor should be as short as possible. 58 Rev. 01 -- 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A400 PACKAGE SPECIFICATIONS BGA256: plastic ball grid array package; 256 balls D D1 B A SOT1018-1 ball A1 index area E1 E A A2 A1 detail X e1 e 1/2 e b v w M M CAB C C y1 C y T R P N M L K J H G F E D C B A e e2 1/2 e ball A1 index area 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 X 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max 1.95 A1 0.5 0.3 A2 1.45 1.25 b 0.55 0.45 D 17.2 16.8 D1 15.75 14.75 E 17.2 16.8 E1 15.75 14.75 e 1 e1 15 e2 15 v 0.25 w 0.1 y 0.15 y1 0.35 OUTLINE VERSION SOT1018-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 07-07-07 07-07-07 Figure 48. Package outline SOT1018-1 (BGA256) Preliminary data sheet Rev. 01 -- 16 July 2007 59 LH7A400 NXP Semiconductors 32-Bit System-on-Chip LFBGA256: plastic low profile fine-pitch ball grid array package; 256 balls D B A SOT1020-1 ball A1 index area E A A2 A1 detail X e1 e 1/2 e b v w M M CAB C C y1 C y T R P N M L K J H G F E D C B A e e2 1/2 e ball A1 index area 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 X 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max 1.7 A1 0.4 0.3 A2 1.35 1.15 b 0.5 0.4 D 14.1 13.9 E 14.1 13.9 e 0.8 e1 12 e2 12 v 0.15 w 0.08 y 0.12 y1 0.1 OUTLINE VERSION SOT1020-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 07-07-07 07-07-07 Figure 49. Package outline SOT1020-1 (LFBGA256) 60 Rev. 01 -- 16 July 2007 Preliminary data sheet 32-Bit System-on-Chip NXP Semiconductors LH7A400 REVISION HISTORY Table 14. Revision history Document ID LH7A400_N_1 Modifications: * First NXP version based on the LH7A400 data sheet of 20070509 Release date Data sheet status 20070716 Preliminary data sheet Change notice Supersedes FAST LH7A400 v1-5 5-9-07 Preliminary data sheet Rev. 01 -- 16 July 2007 61 LH7A400 NXP Semiconductors 32-Bit System-on-Chip 1. Legal information 1.1 Data sheet status Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 1.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 1.3 Disclaimers General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 1.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 2. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com (c) NXP B.V. 2007. All rights reserved. IMPORTANT NOTICE Dear customer, As from June 1st, 2007 NXP Semiconductors has acquired the LH7xxx ARM Microcontrollers from Sharp Microelectronics. The following changes are applicable to the attached data sheet. In data sheets where the previous Sharp or Sharp Corporation references remain, please use the new links as shown below. For www.sharpsma.com use www.nxp.com/microcontrollers for indicated sales addresses use salesaddresses@nxp.com (email) The copyright notice at the bottom of each page (or elsewhere in the document, depending on the version) - Copyright (c) (year) by SHARP Corporation. is replaced with: - (c) NXP B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or phone (details via salesaddresses@nxp.com). Thank you for your cooperation and understanding, In addition to that the Annex A (attached hereto) is added to the document. NXP Semiconductors ANNEX A: Disclaimers (11) 1. t001dis100.fm: General (DS, AN, UM) General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. 2. t001dis101.fm: Right to make changes (DS, AN, UM) Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 3. t001dis102.fm: Suitability for use (DS, AN, UM) Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. 4. t001dis103.fm: Applications (DS, AN, UM) Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 5. t001dis104.fm: Limiting values (DS) Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. 6. t001dis105.fm: Terms and conditions of sale (DS) Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. 7. t001dis106.fm: No offer to sell or license (DS) No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 8. t001dis107.fm: Hazardous voltage (DS, AN, UM; if applicable) Hazardous voltage -- Although basic supply voltages of the product may be much lower, circuit voltages up to 60 V may appear when operating this product, depending on settings and application. Customers incorporating or otherwise using these products in applications where such high voltages may appear during operation, assembly, test etc. of such application, do so at their own risk. Customers agree to fully indemnify NXP Semiconductors for any damages resulting from or in connection with such high voltages. Furthermore, customers are drawn to safety standards (IEC 950, EN 60 950, CENELEC, ISO, etc.) and other (legal) requirements applying to such high voltages. 9. t001dis108.2.fm: Bare die (DS; if applicable) Bare die (if applicable) -- Products indicated as Bare Die are subject to separate specifications and are not tested in accordance with standard testing procedures. Product warranties and guarantees as stated in this document are not applicable to Bare Die Products unless such warranties and guarantees are explicitly stated in a valid separate agreement entered into by NXP Semiconductors and customer. 10. t001dis109.fm: AEC unqualified products (DS, AN, UM; if applicable) AEC unqualified products -- This product has not been qualified to the appropriate Automotive Electronics Council (AEC) standard Q100 or Q101 and should not be used in automotive critical applications, including but not limited to applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is for the customer's own risk. 11. t001dis110.fm: Suitability for use in automotive applications only (DS, AN, UM; if applicable) Suitability for use in automotive applications only -- This NXP Semiconductors product has been developed for use in automotive applications only. The product is not designed, authorized or warranted to be suitable for any other use, including medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. |
Price & Availability of LH7A400N0F000B3A
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |